rtw89_write16_set
rtw89_write16_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE);
rtw89_write16_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14);
rtw89_write16_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15);
rtw89_write16_set(rtwdev, R_BE_SYS_ISO_CTRL, B_BE_PWC_EV2EF_S);
rtw89_write16_set(rtwdev, R_BE_SYS_ISO_CTRL, B_BE_PWC_EV2EF_B);
rtw89_write16_set(rtwdev, R_BE_SYS_ISO_CTRL, B_BE_ISO_EB2CORE);
rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx),
rtw89_write16_set(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_EN);
rtw89_write16_set(rtwdev, reg, B_AX_BT_PLT_RST);
rtw89_write16_set(rtwdev, reg, set);
rtw89_write16_set(rtwdev, reg, B_BE_BUSY_CHKSN);
rtw89_write16_set(rtwdev, reg, B_BE_PLCP_SU_PSDU_LEN_SRC);
rtw89_write16_set(rtwdev, reg, B_BE_BT_PLT_RST);
rtw89_write16_set(rtwdev, R_AX_MDIO_CFG, rw_bit);
rtw89_write16_set(rtwdev, phy_offset + RAC_ANA0D * RAC_MULT, BAC_RX_TEST_EN);
rtw89_write16_set(rtwdev, phy_offset + RAC_ANA19 * RAC_MULT, B_PCIE_BIT_RD_SEL);
rtw89_write16_set(rtwdev, R_RAC_DIRECT_OFFSET_G1 + RAC_ANA09 * RAC_MULT,
rtw89_write16_set(rtwdev, R_RAC_DIRECT_OFFSET_G2 + RAC_ANA09 * RAC_MULT,
rtw89_write16_set(rtwdev, phy_offset + RAC_ANA10 * RAC_MULT,
rtw89_write16_set(rtwdev, phy_offset + RAC_ANA19 * RAC_MULT,
rtw89_write16_set(rtwdev, phy_offset + RAC_ANA0A * RAC_MULT,
rtw89_write16_set(rtwdev,
rtw89_write16_set(rtwdev, phy_offset + RAC_ANA0C * RAC_MULT,
rtw89_write16_set(rtwdev, RAC_DIRECT_OFFESET_L0_G1 +
rtw89_write16_set(rtwdev, RAC_DIRECT_OFFESET_L0_G2 +
rtw89_write16_set(rtwdev, phy_offset + RAC_ANA0D * RAC_MULT,
rtw89_write16_set(rtwdev, phy_offset + RAC_ANA19 * RAC_MULT,
rtw89_write16_set(rtwdev, phy_offset + RAC_ANA09 * RAC_MULT,