rtsx_pci_writel
rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
rtsx_pci_writel(pcr, RTSX_DUM_REG, val | 0x1);
rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
rtsx_pci_writel(pcr, RTSX_BIER, 0);
rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
rtsx_pci_writel(pcr, RTSX_BIER, 0);
rtsx_pci_writel(pcr, RTSX_HAIMR, val);
rtsx_pci_writel(pcr, RTSX_HAIMR, val);
rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
rtsx_pci_writel(pcr, RTSX_HDBAR, pcr->host_sg_tbl_addr);
rtsx_pci_writel(pcr, RTSX_HDBCTLR, val);
rtsx_pci_writel(pcr, RTSX_BIER, pcr->bier);
rtsx_pci_writel(pcr, RTSX_BIPR, int_reg);
rtsx_pci_writel(pcr, RTSX_BIER, pcr->hw_param.interrupt_en);