rtl92s_phy_query_bb_reg
path1 = (u8)(rtl92s_phy_query_bb_reg(hw, RFPGA0_TXINFO, 0xf));
path2 = (u8)(rtl92s_phy_query_bb_reg(hw, ROFDM0_TRXPATHENABLE, 0xf));
rtlphy->cck_high_power = (bool)(rtl92s_phy_query_bb_reg(hw,
u32 rtl92s_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
u4reg_val = rtl92s_phy_query_bb_reg(hw,
u4reg_val = rtl92s_phy_query_bb_reg(hw,
.get_bbreg = rtl92s_phy_query_bb_reg,