arch/arm64/include/asm/kvm_host.h

1657

struct resx get_reg_fixed_bits(struct kvm *kvm, enum vcpu_sysreg reg);

arch/arm64/include/asm/kvm_host.h

652

struct resx mask[NR_SYS_REGS - __SANITISED_REG_START__];

arch/arm64/include/asm/kvm_host.h

655

static inline struct resx __kvm_get_sysreg_resx(struct kvm_arch *arch,

arch/arm64/include/asm/kvm_host.h

665

return (struct resx){};

arch/arm64/include/asm/kvm_host.h

671

enum vcpu_sysreg sr, struct resx resx)

arch/arm64/include/asm/kvm_host.h

673

arch->sysreg_masks->mask[sr - __SANITISED_REG_START__] = resx;

arch/arm64/include/asm/kvm_host.h

676

#define kvm_set_sysreg_resx(k, sr, resx) \

arch/arm64/include/asm/kvm_host.h

677

__kvm_set_sysreg_resx(&(k)->arch, (sr), (resx))

arch/arm64/kvm/config.c

1343

int map_size, u64 resx, const char *str)

arch/arm64/kvm/config.c

1353

if (!((map[i].flags & FORCE_RESx) && (map[i].bits & resx)))

arch/arm64/kvm/config.c

1356

if (mask != ~resx)

arch/arm64/kvm/config.c

1358

str, mask ^ ~resx);

arch/arm64/kvm/config.c

1412

static struct resx compute_resx_bits(struct kvm *kvm,

arch/arm64/kvm/config.c

1419

struct resx resx = {};

arch/arm64/kvm/config.c

1446

resx.res1 |= bits;

arch/arm64/kvm/config.c

1448

resx.res0 |= bits;

arch/arm64/kvm/config.c

1452

return resx;

arch/arm64/kvm/config.c

1455

static struct resx compute_reg_resx_bits(struct kvm *kvm,

arch/arm64/kvm/config.c

1460

struct resx resx;

arch/arm64/kvm/config.c

1462

resx = compute_resx_bits(kvm, r->bit_feat_map, r->bit_feat_map_sz,

arch/arm64/kvm/config.c

1466

resx.res0 |= r->feat_map.masks->res0;

arch/arm64/kvm/config.c

1467

resx.res1 |= r->feat_map.masks->res1;

arch/arm64/kvm/config.c

1476

resx.res0 |= compute_resx_bits(kvm, &r->feat_map, 1, require, exclude).res0;

arch/arm64/kvm/config.c

1477

resx.res1 &= ~resx.res0;

arch/arm64/kvm/config.c

1479

return resx;

arch/arm64/kvm/config.c

1484

struct resx resx;

arch/arm64/kvm/config.c

1492

resx = compute_resx_bits(kvm, r->bit_feat_map, r->bit_feat_map_sz,

arch/arm64/kvm/config.c

1495

return resx.res0 | resx.res1;

arch/arm64/kvm/config.c

1542

struct resx get_reg_fixed_bits(struct kvm *kvm, enum vcpu_sysreg reg)

arch/arm64/kvm/config.c

1544

struct resx resx;

arch/arm64/kvm/config.c

1548

resx = compute_reg_resx_bits(kvm, &hfgrtr_desc, 0, 0);

arch/arm64/kvm/config.c

1551

resx = compute_reg_resx_bits(kvm, &hfgwtr_desc, 0, 0);

arch/arm64/kvm/config.c

1554

resx = compute_reg_resx_bits(kvm, &hfgitr_desc, 0, 0);

arch/arm64/kvm/config.c

1557

resx = compute_reg_resx_bits(kvm, &hdfgrtr_desc, 0, 0);

arch/arm64/kvm/config.c

1560

resx = compute_reg_resx_bits(kvm, &hdfgwtr_desc, 0, 0);

arch/arm64/kvm/config.c

1563

resx = compute_reg_resx_bits(kvm, &hafgrtr_desc, 0, 0);

arch/arm64/kvm/config.c

1566

resx = compute_reg_resx_bits(kvm, &hfgrtr2_desc, 0, 0);

arch/arm64/kvm/config.c

1569

resx = compute_reg_resx_bits(kvm, &hfgwtr2_desc, 0, 0);

arch/arm64/kvm/config.c

1572

resx = compute_reg_resx_bits(kvm, &hfgitr2_desc, 0, 0);

arch/arm64/kvm/config.c

1575

resx = compute_reg_resx_bits(kvm, &hdfgrtr2_desc, 0, 0);

arch/arm64/kvm/config.c

1578

resx = compute_reg_resx_bits(kvm, &hdfgwtr2_desc, 0, 0);

arch/arm64/kvm/config.c

1581

resx = compute_reg_resx_bits(kvm, &hcrx_desc, 0, 0);

arch/arm64/kvm/config.c

1582

resx.res1 |= __HCRX_EL2_RES1;

arch/arm64/kvm/config.c

1585

resx = compute_reg_resx_bits(kvm, &hcr_desc, 0, 0);

arch/arm64/kvm/config.c

1589

resx = compute_reg_resx_bits(kvm, &sctlr2_desc, 0, 0);

arch/arm64/kvm/config.c

1592

resx = compute_reg_resx_bits(kvm, &tcr2_el2_desc, 0, 0);

arch/arm64/kvm/config.c

1595

resx = compute_reg_resx_bits(kvm, &sctlr_el1_desc, 0, 0);

arch/arm64/kvm/config.c

1598

resx = compute_reg_resx_bits(kvm, &sctlr_el2_desc, 0, 0);

arch/arm64/kvm/config.c

1601

resx = compute_reg_resx_bits(kvm, &mdcr_el2_desc, 0, 0);

arch/arm64/kvm/config.c

1604

resx = compute_reg_resx_bits(kvm, &vtcr_el2_desc, 0, 0);

arch/arm64/kvm/config.c

1607

resx = compute_reg_resx_bits(kvm, &ich_hfgrtr_desc, 0, 0);

arch/arm64/kvm/config.c

1610

resx = compute_reg_resx_bits(kvm, &ich_hfgwtr_desc, 0, 0);

arch/arm64/kvm/config.c

1613

resx = compute_reg_resx_bits(kvm, &ich_hfgitr_desc, 0, 0);

arch/arm64/kvm/config.c

1617

resx = (typeof(resx)){};

arch/arm64/kvm/config.c

1621

return resx;

arch/arm64/kvm/nested.c

1775

struct resx resx;

arch/arm64/kvm/nested.c

1777

resx = kvm_get_sysreg_resx(vcpu->kvm, sr);

arch/arm64/kvm/nested.c

1778

v &= ~resx.res0;

arch/arm64/kvm/nested.c

1779

v |= resx.res1;

arch/arm64/kvm/nested.c

1784

static __always_inline void set_sysreg_masks(struct kvm *kvm, int sr, struct resx resx)

arch/arm64/kvm/nested.c

1790

kvm_set_sysreg_resx(kvm, sr, resx);

arch/arm64/kvm/nested.c

1796

struct resx resx;

arch/arm64/kvm/nested.c

1809

resx = (typeof(resx)){};

arch/arm64/kvm/nested.c

1811

resx.res0 |= GENMASK(63, 56);

arch/arm64/kvm/nested.c

1813

resx.res0 |= VTTBR_CNP_BIT;

arch/arm64/kvm/nested.c

1814

set_sysreg_masks(kvm, VTTBR_EL2, resx);

arch/arm64/kvm/nested.c

1817

resx = get_reg_fixed_bits(kvm, VTCR_EL2);

arch/arm64/kvm/nested.c

1818

set_sysreg_masks(kvm, VTCR_EL2, resx);

arch/arm64/kvm/nested.c

1821

resx.res0 = GENMASK(63, 40) | GENMASK(30, 24);

arch/arm64/kvm/nested.c

1822

resx.res1 = BIT(31);

arch/arm64/kvm/nested.c

1823

set_sysreg_masks(kvm, VMPIDR_EL2, resx);

arch/arm64/kvm/nested.c

1826

resx = get_reg_fixed_bits(kvm, HCR_EL2);

arch/arm64/kvm/nested.c

1827

set_sysreg_masks(kvm, HCR_EL2, resx);

arch/arm64/kvm/nested.c

1830

resx = get_reg_fixed_bits(kvm, HCRX_EL2);

arch/arm64/kvm/nested.c

1831

set_sysreg_masks(kvm, HCRX_EL2, resx);

arch/arm64/kvm/nested.c

1834

resx = get_reg_fixed_bits(kvm, HFGRTR_EL2);

arch/arm64/kvm/nested.c

1835

set_sysreg_masks(kvm, HFGRTR_EL2, resx);

arch/arm64/kvm/nested.c

1836

resx = get_reg_fixed_bits(kvm, HFGWTR_EL2);

arch/arm64/kvm/nested.c

1837

set_sysreg_masks(kvm, HFGWTR_EL2, resx);

arch/arm64/kvm/nested.c

1840

resx = get_reg_fixed_bits(kvm, HDFGRTR_EL2);

arch/arm64/kvm/nested.c

1841

set_sysreg_masks(kvm, HDFGRTR_EL2, resx);

arch/arm64/kvm/nested.c

1842

resx = get_reg_fixed_bits(kvm, HDFGWTR_EL2);

arch/arm64/kvm/nested.c

1843

set_sysreg_masks(kvm, HDFGWTR_EL2, resx);

arch/arm64/kvm/nested.c

1846

resx = get_reg_fixed_bits(kvm, HFGITR_EL2);

arch/arm64/kvm/nested.c

1847

set_sysreg_masks(kvm, HFGITR_EL2, resx);

arch/arm64/kvm/nested.c

1850

resx = get_reg_fixed_bits(kvm, HAFGRTR_EL2);

arch/arm64/kvm/nested.c

1851

set_sysreg_masks(kvm, HAFGRTR_EL2, resx);

arch/arm64/kvm/nested.c

1854

resx = get_reg_fixed_bits(kvm, HFGRTR2_EL2);

arch/arm64/kvm/nested.c

1855

set_sysreg_masks(kvm, HFGRTR2_EL2, resx);

arch/arm64/kvm/nested.c

1856

resx = get_reg_fixed_bits(kvm, HFGWTR2_EL2);

arch/arm64/kvm/nested.c

1857

set_sysreg_masks(kvm, HFGWTR2_EL2, resx);

arch/arm64/kvm/nested.c

1860

resx = get_reg_fixed_bits(kvm, HDFGRTR2_EL2);

arch/arm64/kvm/nested.c

1861

set_sysreg_masks(kvm, HDFGRTR2_EL2, resx);

arch/arm64/kvm/nested.c

1862

resx = get_reg_fixed_bits(kvm, HDFGWTR2_EL2);

arch/arm64/kvm/nested.c

1863

set_sysreg_masks(kvm, HDFGWTR2_EL2, resx);

arch/arm64/kvm/nested.c

1866

resx = get_reg_fixed_bits(kvm, HFGITR2_EL2);

arch/arm64/kvm/nested.c

1867

set_sysreg_masks(kvm, HFGITR2_EL2, resx);

arch/arm64/kvm/nested.c

1870

resx = get_reg_fixed_bits(kvm, TCR2_EL2);

arch/arm64/kvm/nested.c

1871

set_sysreg_masks(kvm, TCR2_EL2, resx);

arch/arm64/kvm/nested.c

1874

resx = get_reg_fixed_bits(kvm, SCTLR_EL1);

arch/arm64/kvm/nested.c

1875

set_sysreg_masks(kvm, SCTLR_EL1, resx);

arch/arm64/kvm/nested.c

1878

resx = get_reg_fixed_bits(kvm, SCTLR_EL2);

arch/arm64/kvm/nested.c

1879

set_sysreg_masks(kvm, SCTLR_EL2, resx);

arch/arm64/kvm/nested.c

1882

resx = get_reg_fixed_bits(kvm, SCTLR2_EL1);

arch/arm64/kvm/nested.c

1883

set_sysreg_masks(kvm, SCTLR2_EL1, resx);

arch/arm64/kvm/nested.c

1884

resx = get_reg_fixed_bits(kvm, SCTLR2_EL2);

arch/arm64/kvm/nested.c

1885

set_sysreg_masks(kvm, SCTLR2_EL2, resx);

arch/arm64/kvm/nested.c

1888

resx = get_reg_fixed_bits(kvm, MDCR_EL2);

arch/arm64/kvm/nested.c

1889

set_sysreg_masks(kvm, MDCR_EL2, resx);

arch/arm64/kvm/nested.c

1892

resx.res0 = GENMASK(63, 20);

arch/arm64/kvm/nested.c

1893

resx.res1 = 0;

arch/arm64/kvm/nested.c

1895

resx.res0 |= CNTHCTL_CNTPMASK | CNTHCTL_CNTVMASK;

arch/arm64/kvm/nested.c

1897

resx.res0 |= CNTHCTL_ECV;

arch/arm64/kvm/nested.c

1899

resx.res0 |= (CNTHCTL_EL1TVT | CNTHCTL_EL1TVCT |

arch/arm64/kvm/nested.c

1903

resx.res0 |= GENMASK(11, 8);

arch/arm64/kvm/nested.c

1904

set_sysreg_masks(kvm, CNTHCTL_EL2, resx);

arch/arm64/kvm/nested.c

1907

resx.res0 = ICH_HCR_EL2_RES0;

arch/arm64/kvm/nested.c

1908

resx.res1 = ICH_HCR_EL2_RES1;

arch/arm64/kvm/nested.c

1910

resx.res0 |= ICH_HCR_EL2_TDIR;

arch/arm64/kvm/nested.c

1912

resx.res0 |= ICH_HCR_EL2_DVIM | ICH_HCR_EL2_vSGIEOICount;

arch/arm64/kvm/nested.c

1913

set_sysreg_masks(kvm, ICH_HCR_EL2, resx);

arch/arm64/kvm/nested.c

1916

resx.res0 = VNCR_EL2_RES0;

arch/arm64/kvm/nested.c

1917

resx.res1 = VNCR_EL2_RES1;

arch/arm64/kvm/nested.c

1918

set_sysreg_masks(kvm, VNCR_EL2, resx);

arch/arm64/kvm/nested.c

1921

resx.res0 = ZCR_ELx_RES0 | GENMASK_ULL(8, 4);

arch/arm64/kvm/nested.c

1922

resx.res1 = ZCR_ELx_RES1;

arch/arm64/kvm/nested.c

1923

set_sysreg_masks(kvm, ZCR_EL2, resx);

arch/arm64/kvm/sys_regs.c

5205

struct resx resx;

arch/arm64/kvm/sys_regs.c

5210

resx = kvm_get_sysreg_resx(kvm, desc->reg);

arch/arm64/kvm/sys_regs.c

5213

desc->name, resx.res0, resx.res1);

drivers/input/touchscreen/ili210x.c

379

u16 resx, resy;

drivers/input/touchscreen/ili210x.c

386

resx = le16_to_cpup((__le16 *)rs);

drivers/input/touchscreen/ili210x.c

390

if (!resx || resx == 0xffff || !resy || resy == 0xffff)

drivers/input/touchscreen/ili210x.c

402

resx = 16384;

drivers/input/touchscreen/ili210x.c

406

input_abs_set_max(priv->input, ABS_X, resx - 1);

drivers/input/touchscreen/ili210x.c

408

input_abs_set_max(priv->input, ABS_MT_POSITION_X, resx - 1);