reset_state
struct vcpu_reset_state reset_state;
reset_state->r0 = smccc_get_arg3(source_vcpu);
reset_state->reset = true;
struct vcpu_reset_state *reset_state;
reset_state = &vcpu->arch.reset_state;
reset_state->pc = smccc_get_arg2(source_vcpu);
reset_state->be = kvm_vcpu_is_be(source_vcpu);
struct vcpu_reset_state reset_state;
reset_state = vcpu->arch.reset_state;
vcpu->arch.reset_state.reset = false;
if (reset_state.reset) {
unsigned long target_pc = reset_state.pc;
if (reset_state.be)
vcpu_set_reg(vcpu, 0, reset_state.r0);
int reset_state = (EEH_PE_RESET | EEH_PE_CFG_BLOCKED);
eeh_pe_state_mark(pe, reset_state);
eeh_pe_state_clear(pe, reset_state, true);
struct kvm_vcpu_reset_state reset_state;
spin_lock_init(&vcpu->arch.reset_state.lock);
spin_lock(&vcpu->arch.reset_state.lock);
vcpu->arch.reset_state.pc = pc;
vcpu->arch.reset_state.a1 = a1;
spin_unlock(&vcpu->arch.reset_state.lock);
struct kvm_vcpu_reset_state *reset_state = &vcpu->arch.reset_state;
spin_lock(&vcpu->arch.reset_state.lock);
cntx->sepc = reset_state->pc;
cntx->a1 = reset_state->a1;
spin_unlock(&vcpu->arch.reset_state.lock);
dom->reset_state = cpu_to_le32(state);
r->reset_state = le32_to_cpu(p->reset_state);
__le32 reset_state;
__le32 reset_state;
u32 id, u32 reset_state)
req->resets = reset_state;
u32 id, u32 *reset_state)
return ti_sci_get_device_state(handle, id, NULL, reset_state, NULL,
uint8_t reset_state : 1;
if (priv->handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT) {
reset_stage = handle->rinfo.reset_state;
if (handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT ||
if (priv->handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT ||
handle->rinfo.reset_state = HNS_ROCE_STATE_RST_DOWN;
handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED;
handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INIT;
handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED;
handle->rinfo.reset_state = HNS_ROCE_STATE_RST_UNINIT;
unsigned long reset_state;
set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state);
&hdev->reset_state)) {
&hdev->reset_state)) {
set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
unsigned long reset_state; /* requested, pending */
set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
struct ibmvnic_rwi *rwi, u32 reset_state)
adapter_state_to_string(reset_state));
reset_state = adapter->state;
if (reset_state == VNIC_REMOVING || reset_state == VNIC_REMOVED) {
if (reset_state == VNIC_OPEN &&
adapter_state_to_string(reset_state));
reset_state = VNIC_OPEN;
if (reset_state == VNIC_PROBED || reset_state == VNIC_DOWN) {
if (reset_state == VNIC_CLOSED) {
adapter->state = reset_state;
struct ibmvnic_rwi *rwi, u32 reset_state)
reset_state = adapter->state;
if (reset_state == VNIC_REMOVING || reset_state == VNIC_REMOVED) {
if (reset_state == VNIC_PROBED || reset_state == VNIC_DOWN)
if (reset_state == VNIC_CLOSED)
adapter->state = reset_state;
u32 reset_state;
reset_state = adapter->state;
rc = do_hard_reset(adapter, rwi, reset_state);
rc = do_hard_reset(adapter, rwi, reset_state);
rc = do_reset(adapter, rwi, reset_state);
u8 *reset_type, u8 *reset_state, u8 *reset_method)
if (reset_state)
*reset_state = MLX5_GET(mfrl_reg, out, reset_state);
u8 reset_state;
if (mlx5_reg_mfrl_query(dev, NULL, NULL, &reset_state, NULL))
if (!reset_state)
switch (reset_state) {
if (err == -EREMOTEIO && MLX5_CAP_MCAM_FEATURE(dev, reset_state)) {
mdiodev->reset_state = value;
mdiodev->reset_state = -1;
if (mdiodev->reset_state == value)
mdiodev->reset_state = -1;
dev->reset_state = mcu_int;
u32 reset_state;
(READ_ONCE(dev->reset_state) & state),
if (!(READ_ONCE(dev->reset_state) & MT_MCU_CMD_STOP_PDMA))
u32 reset_state;
ret = dev_ops->get_device_resets(sci, control->dev_id, &reset_state);
return reset_state & control->reset_mask;
u32 reset_state;
ret = dev_ops->get_device_resets(sci, control->dev_id, &reset_state);
reset_state |= control->reset_mask;
reset_state &= ~control->reset_mask;
ret = dev_ops->set_device_resets(sci, control->dev_id, reset_state);
unsigned int reset_state;
ret = regmap_read(data->regmap, control->status_offset, &reset_state);
return !(reset_state & BIT(control->status_bit)) ==
s8 reset_state; /* 0 - no reset, 1..x - */
info->reset_state = 2;
info->reset_state = 0;
if (info->reset_state <= 0) {
ret = info->reset_state == 0 ? SUCCESS : FAILED;
info->reset_state = 0;
info->reset_state = res;
!(info->reset_state > 0)))
info->reset_state = 1;
info->reset_state = 0;
if (info->reset_state == 0) {
ret = info->reset_state == 0 ? SUCCESS : FAILED;
!(info->reset_state > 0)))
reset_state(STp); /* Clears pos_unknown */
reset_state(STp);
gpio_latch = (u8)((le16_to_cpu(config.reset_state) &
priv->gpio_pushpull = le16_to_cpu(config.reset_state.gpio_mode_pb1);
gpio_latch = le16_to_cpu(config.reset_state.gpio_latch_pb1);
__le16 reset_state;
__le16 reset_state;
struct cp210x_quad_port_state reset_state;
st = &mdsc->reset_state;
struct ceph_client_reset_state *st = &mdsc->reset_state;
struct ceph_client_reset_state *st = &mdsc->reset_state;
struct ceph_client_reset_state *st = &mdsc->reset_state;
struct ceph_client_reset_state *st = &mdsc->reset_state;
spin_lock_init(&mdsc->reset_state.lock);
init_waitqueue_head(&mdsc->reset_state.blocked_wq);
atomic_set(&mdsc->reset_state.blocked_requests, 0);
spin_lock(&mdsc->reset_state.lock);
mdsc->reset_state.shutdown = true;
if (mdsc->reset_state.phase != CEPH_CLIENT_RESET_IDLE) {
mdsc->reset_state.phase = CEPH_CLIENT_RESET_IDLE;
mdsc->reset_state.last_errno = -ESHUTDOWN;
mdsc->reset_state.last_finish = jiffies;
mdsc->reset_state.failure_count++;
spin_unlock(&mdsc->reset_state.lock);
wake_up_all(&mdsc->reset_state.blocked_wq);
struct ceph_client_reset_state reset_state;
int reset_state;
u8 reset_state[0x1];
u8 reset_state[0x4];
unsigned int reset_state;
u32 reset_state);
u32 *reset_state);
u8 reset_state;
chip->reset_state = snd_m3_inb(chip, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK;
snd_m3_outb(chip, chip->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
snd_m3_outb(chip, chip->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
enum timer_view tv, irq_wait_method_t wm, bool reset_state,
if (reset_state)
irq_wait_method_t wm, bool reset_state,
test_timer_xval(timer, cval, TIMER_CVAL, wm, reset_state, reset_cnt);
irq_wait_method_t wm, bool reset_state,
test_timer_xval(timer, (u64)tval, TIMER_TVAL, wm, reset_state,