reset_flags
u32 index, ctl, reset_flags = 0, error_count = 0;
reset_flags |= HL_DRV_RESET_FW_FATAL_ERR;
reset_flags |= HL_DRV_RESET_FW_FATAL_ERR;
reset_flags |= HL_DRV_RESET_FW_FATAL_ERR;
reset_flags |= HL_DRV_RESET_FW_FATAL_ERR;
reset_flags |= HL_DRV_RESET_FW_FATAL_ERR;
reset_flags |= HL_DRV_RESET_FW_FATAL_ERR;
reset_flags |= HL_DRV_RESET_FW_FATAL_ERR;
reset_flags |= HL_DRV_RESET_FW_FATAL_ERR;
reset_flags |= HL_DRV_RESET_FW_FATAL_ERR;
reset_flags |= HL_DRV_RESET_FW_FATAL_ERR;
reset_flags |= HL_DRV_RESET_FW_FATAL_ERR;
reset_flags |= HL_DRV_RESET_FW_FATAL_ERR;
reset_flags |= HL_DRV_RESET_FW_FATAL_ERR;
reset_flags |= HL_DRV_RESET_FW_FATAL_ERR;
reset_flags |= HL_DRV_RESET_FW_FATAL_ERR;
reset_flags |= HL_DRV_RESET_FW_FATAL_ERR;
reset_flags |= HL_DRV_RESET_FW_FATAL_ERR;
reset_flags |= HL_DRV_RESET_HARD;
reset_flags |= HL_DRV_RESET_BYPASS_REQ_TO_FW;
reset_flags |= HL_DRV_RESET_DELAY;
hl_device_cond_reset(hdev, reset_flags, event_mask);
reset_flags(bt); /* next state is now IDLE */
reset_flags(bt);
reset_flags(bt);
(adev->gmc.reset_flags & AMDGPU_GMC_INIT_RESET_NPS);
uint32_t reset_flags;
uint32_t reset_flags = 0, reset = 0;
reset_flags |= msg.reset;
if (reset_flags && !amdgpu_ras_is_rma(adev)) {
if (reset_flags & AMDGPU_RAS_GPU_RESET_MODE1_RESET)
else if (reset_flags & AMDGPU_RAS_GPU_RESET_MODE2_RESET)
reset = reset_flags;
adev->gmc.reset_flags |= AMDGPU_GMC_INIT_RESET_NPS;
if (adev->gmc.reset_flags & AMDGPU_GMC_INIT_RESET_NPS) {
adev->gmc.reset_flags &= ~AMDGPU_GMC_INIT_RESET_NPS;
uint32_t reset_flags = 0;
reset_flags |= req.reset;
if (reset_flags) {
RAS_EVENT_ID__RESET_GPU, &reset_flags);
if (!ret && (reset_flags & GPU_RESET_CAUSE_RMA))
void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags);
void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired);
u32 reset_flags = 0;
reset_flags |= BIT(__I40E_REINIT_REQUESTED);
reset_flags |= BIT(__I40E_PF_RESET_REQUESTED);
reset_flags |= BIT(__I40E_CORE_RESET_REQUESTED);
reset_flags |= BIT(__I40E_GLOBAL_RESET_REQUESTED);
reset_flags |= BIT(__I40E_DOWN_REQUESTED);
if (reset_flags &&
i40e_do_reset(pf, reset_flags, false);
void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired)
if (reset_flags & BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED)) {
} else if (reset_flags & BIT_ULL(__I40E_CORE_RESET_REQUESTED)) {
} else if (reset_flags & I40E_PF_RESET_FLAG) {
} else if (reset_flags & I40E_PF_RESET_AND_REBUILD_FLAG) {
} else if (reset_flags & BIT_ULL(__I40E_REINIT_REQUESTED)) {
} else if (reset_flags & BIT_ULL(__I40E_DOWN_REQUESTED)) {
"bad reset request 0x%08x\n", reset_flags);
void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
i40e_do_reset(pf, reset_flags, true);
return test_bit(MLX5_FW_RESET_FLAGS_RESET_IN_PROGRESS, &fw_reset->reset_flags);
set_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags);
clear_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags);
if (test_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags)) {
clear_bit(MLX5_FW_RESET_FLAGS_RESET_IN_PROGRESS, &fw_reset->reset_flags);
if (!test_and_clear_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags)) {
if (!test_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags))
if (!test_bit(MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, &fw_reset->reset_flags))
unsigned long reset_flags;
if (test_and_set_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags)) {
&fw_reset->reset_flags))
&fw_reset->reset_flags)) {
&fw_reset->reset_flags) &&
set_bit(MLX5_FW_RESET_FLAGS_RESET_IN_PROGRESS, &fw_reset->reset_flags);
if (!test_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags))
if (!test_bit(MLX5_FW_RESET_FLAGS_UNLOAD_EVENT, &fw_reset->reset_flags))
clear_bit(MLX5_FW_RESET_FLAGS_UNLOAD_EVENT, &fw_reset->reset_flags);
clear_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags);
set_bit(MLX5_FW_RESET_FLAGS_RELOAD_REQUIRED, &fw_reset->reset_flags);
set_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags);
set_bit(MLX5_FW_RESET_FLAGS_UNLOAD_EVENT, &fw_reset->reset_flags);
clear_bit(MLX5_FW_RESET_FLAGS_RESET_IN_PROGRESS, &fw_reset->reset_flags);
clear_bit(MLX5_FW_RESET_FLAGS_RESET_IN_PROGRESS, &fw_reset->reset_flags);
if (test_bit(MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, &fw_reset->reset_flags))
if (test_and_clear_bit(MLX5_FW_RESET_FLAGS_RELOAD_REQUIRED, &fw_reset->reset_flags)) {
clear_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags);
&fw_reset->reset_flags);
set_bit(MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, &fw_reset->reset_flags);
if (test_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags))
u32 reset_flags)
PM_WRITE(pm_reg, PM_READ(pm_reg) | reset_flags);
PM_WRITE(pm_reg, PM_READ(pm_reg) & ~reset_flags);
u32 reset_flags)
PM_WRITE(pm_reg, PM_READ(pm_reg) & ~reset_flags);
long reset_flags;
&instance->reset_flags))
if (test_bit(MEGASAS_FUSION_IN_RESET, &instance->reset_flags)) {
set_bit(MEGASAS_FUSION_IN_RESET, &instance->reset_flags);
set_bit(MEGASAS_FUSION_OCR_NOT_POSSIBLE, &instance->reset_flags);
&instance->reset_flags);
clear_bit(MEGASAS_FUSION_IN_RESET, &instance->reset_flags);
clear_bit(MEGASAS_FUSION_OCR_NOT_POSSIBLE, &instance->reset_flags);