reset_done
.reset_done = hl_pci_reset_done,
.reset_done = ivpu_pm_reset_done_cb,
.reset_done = qaic_pci_reset_done,
.reset_done = virtblk_reset_done,
.reset_done = mhi_pci_reset_done,
if (cdx_drv && cdx_drv->reset_done)
cdx_drv->reset_done(cdx_dev);
.reset_done = hisi_qm_reset_done,
.reset_done = hisi_qm_reset_done,
.reset_done = hisi_qm_reset_done,
return reset_done(pdev);
reset_done(pdev);
.reset_done = adf_reset_done,
.reset_done = cxl_reset_done,
.reset_done = idxd_reset_done,
struct completion *reset_done);
.reset_done = ipu6_pci_reset_done,
u8 reset_done;
reset_done = val & BIT(TOP_IRQ_STATUS_RESET_DONE);
if (reset_done)
u8 reset_done;
reset_done = val & TOP_IRQ_STATUS_RESET_DONE;
if (reset_done)
if (md->reset_done & type)
md->reset_done |= type;
md->reset_done &= ~type;
unsigned int reset_done;
.reset_done = pdsc_reset_done,
.reset_done = eeh_reset_done,
.reset_done = hbg_pci_err_reset_done,
void (*reset_done)(struct hnae3_ae_dev *ae_dev);
if (ae_dev->ops && ae_dev->ops->reset_done)
ae_dev->ops->reset_done(ae_dev);
if (ae_dev && ae_dev->ops && ae_dev->ops->reset_done)
ae_dev->ops->reset_done(ae_dev);
.reset_done = hns3_reset_done,
.reset_done = hclge_reset_done,
.reset_done = hclgevf_reset_done,
complete(&adapter->reset_done);
reinit_completion(&adapter->reset_done);
rc = ibmvnic_wait_for_completion(adapter, &adapter->reset_done, 60000);
reinit_completion(&adapter->reset_done);
rc = ibmvnic_wait_for_completion(adapter, &adapter->reset_done,
init_completion(&adapter->reset_done);
struct completion reset_done;
.reset_done = fm10k_io_reset_done,
.reset_done = i40e_pci_error_reset_done,
.reset_done = ice_pci_err_reset_done,
.reset_done = igbvf_io_reset_done,
.reset_done = mlxsw_pci_reset_done,
.reset_done = ionic_reset_done,
bool reset_done;
reset_done =
reset_done = inta_hw & CSR_INT_BIT_RESET_DONE;
inta_hw, reset_done);
if (!reset_done && dump_on_timeout) {
.reset_done = mwifiex_pcie_reset_done,
.reset_done = nvme_reset_done,
if (err_handler && err_handler->reset_done)
err_handler->reset_done(dev);
static void reset_done(struct scsi_cmnd *SCpnt)
reset_done(SCpnt);
.reset_done = hisi_sas_reset_done_v3_hw,
.reset_done = qla_pci_reset_done,
.reset_done = ipu7_pci_reset_done,
(fotg210->reset_done[0] &&
time_after_eq(jiffies, fotg210->reset_done[0]))) {
fotg210->reset_done[wIndex] = jiffies
if (!fotg210->reset_done[wIndex]) {
fotg210->reset_done[wIndex] = jiffies
fotg210->reset_done[wIndex]);
fotg210->reset_done[wIndex])) {
fotg210->reset_done[wIndex] = 0;
fotg210->reset_done[wIndex])) {
fotg210->reset_done[wIndex] = 0;
fotg210->reset_done[wIndex] = 0;
fotg210->reset_done[wIndex] = 0;
fotg210->reset_done[wIndex] = jiffies
fotg210->reset_done[0] == 0) {
fotg210->reset_done[0] = jiffies + msecs_to_jiffies(25);
mod_timer(&hcd->rh_timer, fotg210->reset_done[0]);
unsigned long reset_done[FOTG210_MAX_ROOT_PORTS];
ehci->reset_done[wIndex-1] &&
time_after_eq(jiffies, ehci->reset_done[wIndex-1]) &&
ehci->reset_done[i] == 0))
ehci->reset_done[i] = jiffies +
mod_timer(&hcd->rh_timer, ehci->reset_done[i]);
ehci->reset_done[wIndex] = 0;
ehci->reset_done [wIndex] = jiffies
|| (ehci->reset_done[i] && time_after_eq(
jiffies, ehci->reset_done[i]))
ehci->reset_done[wIndex] = jiffies
if (!ehci->reset_done[wIndex]) {
ehci->reset_done[wIndex] = jiffies
ehci->reset_done[wIndex]);
} else if (!time_after_eq(jiffies, ehci->reset_done[wIndex])) {
ehci->reset_done[wIndex] = 0;
ehci->reset_done [wIndex] = 0;
unsigned long reset_done[EHCI_MAX_ROOT_PORTS];
u16 reset_done = now + PORT_RESET_MSEC;
} while (tick_before(now, reset_done) && --limit_1 >= 0);
|| oxu->reset_done[i] != 0)
oxu->reset_done[i] = jiffies +
mod_timer(&hcd->rh_timer, oxu->reset_done[i]);
oxu->reset_done[i] = 0;
time_after_eq(jiffies, oxu->reset_done[i]))) {
oxu->reset_done[wIndex] = jiffies
if (!oxu->reset_done[wIndex]) {
oxu->reset_done[wIndex] = jiffies
oxu->reset_done[wIndex]);
oxu->reset_done[wIndex])) {
oxu->reset_done[wIndex] = 0;
oxu->reset_done[wIndex])) {
oxu->reset_done[wIndex] = 0;
oxu->reset_done[wIndex] = jiffies
oxu->reset_done[i] = jiffies + msecs_to_jiffies(20);
unsigned long reset_done[EHCI_MAX_ROOT_PORTS];
oxu->reset_done[index] = 0;
goto reset_done;
reset_done:
time_after_eq(jiffies, priv->reset_done))) {
priv->reset_done = jiffies +
if (!priv->reset_done) {
priv->reset_done = jiffies
mod_timer(&hcd->rh_timer, priv->reset_done);
priv->reset_done)) {
priv->reset_done = 0;
time_after_eq(jiffies, priv->reset_done)) {
priv->reset_done = 0;
priv->reset_done = jiffies +
unsigned long reset_done;
.reset_done = hisi_acc_vf_pci_aer_reset_done,
.reset_done = mlx5vf_pci_aer_reset_done,
nvdev->reset_done = true;
.reset_done = nvgrace_gpu_vfio_pci_reset_done,
if (!nvdev->reset_done)
nvdev->reset_done = false;
if (nvdev->cxl_dvsec && READ_ONCE(nvdev->reset_done) &&
bool reset_done;
if (nvdev->cxl_dvsec && READ_ONCE(nvdev->reset_done)) {
if (nvdev->cxl_dvsec && READ_ONCE(nvdev->reset_done)) {
.reset_done = pds_vfio_pci_aer_reset_done,
.reset_done = qat_vf_pci_aer_reset_done,
bool reset_done = false;
reset_done = true;
if (reset_done)
.reset_done = virtiovf_pci_aer_reset_done,
.reset_done = xe_vfio_pci_reset_done,
ret = drv->reset_done(dev);
if (!drv || !drv->reset_done)
.reset_done = virtio_pci_reset_done,
void (*reset_done)(struct cdx_device *dev);
void (*reset_done)(struct pci_dev *dev);
int (*reset_done)(struct virtio_device *dev);
bool reset_done = false;
if (!reset_done && orig_prefered_lft > 0) {
reset_done = true;