drivers/ata/sata_fsl.c

1004

iowrite32(1, CQ + hcr_base);

drivers/ata/sata_fsl.c

1238

ioread32(hcr_base + CQ),

drivers/ata/sata_fsl.c

399

if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) {

drivers/ata/sata_fsl.c

548

ioread32(CQ + hcr_base),

drivers/ata/sata_fsl.c

555

iowrite32(1 << tag, CQ + hcr_base);

drivers/ata/sata_fsl.c

558

tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base));

drivers/ata/sata_fsl.c

637

ioread32(CQ + hcr_base),

drivers/ata/sata_fsl.c

960

ioread32(CQ + hcr_base),

drivers/ata/sata_fsl.c

966

iowrite32(1, CQ + hcr_base);

drivers/ata/sata_fsl.c

968

temp = ata_wait_register(ap, CQ + hcr_base, 0x1, 0x1, 1, 5000);

drivers/ata/sata_fsl.c

973

ioread32(CQ + hcr_base),

drivers/infiniband/hw/usnic/usnic_vnic.h

46

DEFINE_USNIC_VNIC_RES(CQ, RES_TYPE_CQ, "CQ") \

drivers/iommu/riscv/iommu.c

1618

RISCV_IOMMU_QUEUE_INIT(&iommu->cmdq, CQ);

drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h

379

#define GLTCLAN_CQ_CNTX(i, CQ) (GLTCLAN_CQ_CNTX0(CQ) + ((i) * 0x0800))

drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c

25

#define CQE_ADDR(CQ, idx) ((CQ)->cqe_base + ((CQ)->cqe_size * (idx)))