arch/mips/pci/pci-mt7620.c

235

rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);

arch/mips/pci/pci-mt7620.c

236

rt_sysc_m32(LC_CKDRVPD, PDRV_SW_SET, PPLL_DRV);

arch/mips/pci/pci-mt7620.c

240

rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);

arch/mips/pci/pci-mt7620.c

246

rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);

arch/mips/pci/pci-mt7620.c

251

rt_sysc_m32(LC_CKDRVHZ | LC_CKDRVOHZ, LC_CKDRVPD | PDRV_SW_SET,

arch/mips/pci/pci-mt7620.c

262

rt_sysc_m32(BIT(16), 0, RALINK_GPIOMODE);

arch/mips/pci/pci-mt7620.c

266

rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);

arch/mips/pci/pci-mt7620.c

327

rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);

arch/mips/pci/pci-mt7620.c

329

rt_sysc_m32(LC_CKDRVPD, PDRV_SW_SET, PPLL_DRV);

arch/mips/ralink/reset.c

27

rt_sysc_m32(0, RSTCTL_RESET_PCI, SYSC_REG_RESET_CTRL);