req_type - Linux

arch/arm/mach-versatile/spc.c

303

static int ve_spc_waitforcompletion(int req_type)

arch/arm/mach-versatile/spc.c

310

ret = info->cur_rsp_stat & STAT_COMPLETE(req_type) ? 0 : -EIO;

arch/arm/mach-versatile/spc.c

317

int ret, perf, req_type;

arch/arm/mach-versatile/spc.c

320

req_type = CA15_DVFS;

arch/arm/mach-versatile/spc.c

323

req_type = CA7_DVFS;

arch/arm/mach-versatile/spc.c

336

info->cur_rsp_mask = RESPONSE_MASK(req_type);

arch/arm/mach-versatile/spc.c

339

ret = ve_spc_waitforcompletion(req_type);

arch/x86/mm/pat/memtype.c

363

enum page_cache_mode req_type)

arch/x86/mm/pat/memtype.c

369

if (req_type == _PAGE_CACHE_MODE_WB) {

arch/x86/mm/pat/memtype.c

379

return req_type;

arch/x86/mm/pat/memtype.c

437

enum page_cache_mode req_type,

arch/x86/mm/pat/memtype.c

443

if (req_type == _PAGE_CACHE_MODE_WP) {

arch/x86/mm/pat/memtype.c

449

if (req_type == _PAGE_CACHE_MODE_UC) {

arch/x86/mm/pat/memtype.c

452

req_type = _PAGE_CACHE_MODE_UC_MINUS;

arch/x86/mm/pat/memtype.c

462

start, end - 1, type, req_type);

arch/x86/mm/pat/memtype.c

471

*new_type = req_type;

arch/x86/mm/pat/memtype.c

475

set_page_memtype(page, req_type);

arch/x86/mm/pat/memtype.c

521

int memtype_reserve(u64 start, u64 end, enum page_cache_mode req_type,

arch/x86/mm/pat/memtype.c

538

start, end - 1, cattr_name(req_type));

arch/x86/mm/pat/memtype.c

545

*new_type = req_type;

arch/x86/mm/pat/memtype.c

562

actual_type = pat_x_mtrr_type(start, end, req_type);

arch/x86/mm/pat/memtype.c

570

err = reserve_ram_pages_type(start, end, req_type, new_type);

arch/x86/mm/pat/memtype.c

591

cattr_name(entry_new->type), cattr_name(req_type));

arch/x86/mm/pat/memtype.c

601

start, end - 1, cattr_name(entry_new->type), cattr_name(req_type),

arch/x86/mm/pat/memtype.c

717

enum page_cache_mode req_type = *type;

arch/x86/mm/pat/memtype.c

723

ret = memtype_reserve(start, end, req_type, &new_type);

arch/x86/mm/pat/memtype.c

727

if (!is_new_memtype_allowed(start, size, req_type, new_type))

drivers/acpi/nfit/core.c

2376

struct nfit_spa *nfit_spa, enum nfit_ars_state req_type)

drivers/acpi/nfit/core.c

2387

if (req_type == ARS_REQ_SHORT)

drivers/acpi/nfit/core.c

2858

enum nfit_ars_state req_type;

drivers/acpi/nfit/core.c

2866

req_type = ARS_REQ_SHORT;

drivers/acpi/nfit/core.c

2868

req_type = ARS_REQ_LONG;

drivers/acpi/nfit/core.c

2871

rc = ars_start(acpi_desc, nfit_spa, req_type);

drivers/acpi/nfit/core.c

2876

req_type == ARS_REQ_SHORT ? "short" : "long",

drivers/acpi/nfit/core.c

2888

clear_bit(req_type, &nfit_spa->ars_state);

drivers/acpi/nfit/core.c

3228

enum nfit_ars_state req_type)

drivers/acpi/nfit/core.c

3248

if (test_and_set_bit(req_type, &nfit_spa->ars_state))

drivers/acpi/nfit/nfit.h

310

enum nfit_ars_state req_type);

drivers/clocksource/timer-ti-dm.c

533

static struct dmtimer *_omap_dm_timer_request(int req_type, void *data)

drivers/clocksource/timer-ti-dm.c

541

switch (req_type) {

drivers/clocksource/timer-ti-dm.c

561

switch (req_type) {

drivers/crypto/hisilicon/zip/zip_crypto.c

201

static void hisi_zip_fill_req_type(struct hisi_zip_sqe *sqe, u8 req_type)

drivers/crypto/hisilicon/zip/zip_crypto.c

206

val |= FIELD_PREP(HZIP_REQ_TYPE_M, req_type);

drivers/crypto/hisilicon/zip/zip_crypto.c

235

u8 req_type, struct hisi_zip_req *req)

drivers/crypto/hisilicon/zip/zip_crypto.c

244

ops->fill_req_type(sqe, req_type);

drivers/crypto/hisilicon/zip/zip_crypto.c

283

hisi_zip_fill_sqe(qp_ctx->ctx, &zip_sqe, qp_ctx->req_type, req);

drivers/crypto/hisilicon/zip/zip_crypto.c

418

static int hisi_zip_ctx_init(struct hisi_zip_ctx *hisi_zip_ctx, u8 req_type, int node)

drivers/crypto/hisilicon/zip/zip_crypto.c

442

qp_ctx->req_type = req_type;

drivers/crypto/hisilicon/zip/zip_crypto.c

74

u8 req_type;

drivers/crypto/hisilicon/zip/zip_crypto.c

82

void (*fill_req_type)(struct hisi_zip_sqe *sqe, u8 req_type);

drivers/crypto/marvell/octeontx/otx_cptvf_algs.c

1152

req_info->req_type = reg_type;

drivers/crypto/marvell/octeontx/otx_cptvf_algs.c

133

if (cpt_req->req_type == OTX_CPT_AEAD_ENC_DEC_NULL_REQ &&

drivers/crypto/marvell/octeontx/otx_cptvf_algs.c

369

req_info->req_type = OTX_CPT_ENC_DEC_REQ;

drivers/crypto/marvell/octeontx/otx_cptvf_reqmgr.h

169

u8 req_type; /* Type of request */

drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h

140

u8 req_type; /* Type of request */

drivers/crypto/marvell/octeontx2/otx2_cptvf_algs.c

116

if (cpt_req->req_type ==

drivers/crypto/marvell/octeontx2/otx2_cptvf_algs.c

1253

req_info->req_type = reg_type;

drivers/crypto/marvell/octeontx2/otx2_cptvf_algs.c

384

req_info->req_type = OTX2_CPT_ENC_DEC_REQ;

drivers/dma/sprd-dma.c

593

enum sprd_dma_req_mode req_type;

drivers/dma/sprd-dma.c

612

req_type = sprd_dma_get_req_type(schan);

drivers/dma/sprd-dma.c

621

trans_done = sprd_dma_check_trans_done(int_type, req_type);

drivers/fwctl/bnxt/main.c

158

switch (le16_to_cpu(req->req_type)) {

drivers/fwctl/bnxt/main.c

69

switch (le16_to_cpu(req->req_type)) {

drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c

741

atcs_input.req_type = ATCS_PCIE_LINK_SPEED;

drivers/gpu/drm/amd/include/amd_acpi.h

99

u8 req_type; /* request type */

drivers/gpu/drm/display/drm_dp_mst_topology.c

102

static const char *drm_dp_mst_req_type_str(u8 req_type)

drivers/gpu/drm/display/drm_dp_mst_topology.c

1043

msg->req_type = (raw->msg[0] & 0x7f);

drivers/gpu/drm/display/drm_dp_mst_topology.c

1052

switch (msg->req_type) {

drivers/gpu/drm/display/drm_dp_mst_topology.c

1078

msg->req_type, drm_dp_mst_req_type_str(msg->req_type));

drivers/gpu/drm/display/drm_dp_mst_topology.c

1142

msg->req_type = (raw->msg[0] & 0x7f);

drivers/gpu/drm/display/drm_dp_mst_topology.c

1144

switch (msg->req_type) {

drivers/gpu/drm/display/drm_dp_mst_topology.c

1151

msg->req_type, drm_dp_mst_req_type_str(msg->req_type));

drivers/gpu/drm/display/drm_dp_mst_topology.c

1161

req.req_type = DP_REMOTE_DPCD_WRITE;

drivers/gpu/drm/display/drm_dp_mst_topology.c

1173

req.req_type = DP_LINK_ADDRESS;

drivers/gpu/drm/display/drm_dp_mst_topology.c

1181

req.req_type = DP_CLEAR_PAYLOAD_ID_TABLE;

drivers/gpu/drm/display/drm_dp_mst_topology.c

1191

req.req_type = DP_ENUM_PATH_RESOURCES;

drivers/gpu/drm/display/drm_dp_mst_topology.c

1207

req.req_type = DP_ALLOCATE_PAYLOAD;

drivers/gpu/drm/display/drm_dp_mst_topology.c

1224

req.req_type = DP_POWER_UP_PHY;

drivers/gpu/drm/display/drm_dp_mst_topology.c

1226

req.req_type = DP_POWER_DOWN_PHY;

drivers/gpu/drm/display/drm_dp_mst_topology.c

123

if (req_type >= ARRAY_SIZE(req_type_str) ||

drivers/gpu/drm/display/drm_dp_mst_topology.c

1239

req.req_type = DP_QUERY_STREAM_ENC_STATUS;

drivers/gpu/drm/display/drm_dp_mst_topology.c

124

!req_type_str[req_type])

drivers/gpu/drm/display/drm_dp_mst_topology.c

127

return req_type_str[req_type];

drivers/gpu/drm/display/drm_dp_mst_topology.c

2725

req.req_type = DP_REMOTE_DPCD_READ;

drivers/gpu/drm/display/drm_dp_mst_topology.c

2767

u8 req_type;

drivers/gpu/drm/display/drm_dp_mst_topology.c

2769

req_type = txmsg->msg[0] & 0x7f;

drivers/gpu/drm/display/drm_dp_mst_topology.c

2770

if (req_type == DP_CONNECTION_STATUS_NOTIFY ||

drivers/gpu/drm/display/drm_dp_mst_topology.c

2771

req_type == DP_RESOURCE_STATUS_NOTIFY ||

drivers/gpu/drm/display/drm_dp_mst_topology.c

2772

req_type == DP_CLEAR_PAYLOAD_ID_TABLE)

drivers/gpu/drm/display/drm_dp_mst_topology.c

352

buf[idx++] = req->req_type & 0x7f;

drivers/gpu/drm/display/drm_dp_mst_topology.c

354

switch (req->req_type) {

drivers/gpu/drm/display/drm_dp_mst_topology.c

3551

static int drm_dp_encode_up_ack_reply(struct drm_dp_sideband_msg_tx *msg, u8 req_type)

drivers/gpu/drm/display/drm_dp_mst_topology.c

3556

reply.req_type = req_type;

drivers/gpu/drm/display/drm_dp_mst_topology.c

3563

int req_type, bool broadcast)

drivers/gpu/drm/display/drm_dp_mst_topology.c

3572

drm_dp_encode_up_ack_reply(txmsg, req_type);

drivers/gpu/drm/display/drm_dp_mst_topology.c

4016

txmsg->reply.req_type,

drivers/gpu/drm/display/drm_dp_mst_topology.c

4017

drm_dp_mst_req_type_str(txmsg->reply.req_type),

drivers/gpu/drm/display/drm_dp_mst_topology.c

4067

if (msg->req_type == DP_CONNECTION_STATUS_NOTIFY)

drivers/gpu/drm/display/drm_dp_mst_topology.c

4069

else if (msg->req_type == DP_RESOURCE_STATUS_NOTIFY)

drivers/gpu/drm/display/drm_dp_mst_topology.c

4084

if (msg->req_type == DP_CONNECTION_STATUS_NOTIFY) {

drivers/gpu/drm/display/drm_dp_mst_topology.c

4152

if (up_req->msg.req_type != DP_CONNECTION_STATUS_NOTIFY &&

drivers/gpu/drm/display/drm_dp_mst_topology.c

4153

up_req->msg.req_type != DP_RESOURCE_STATUS_NOTIFY) {

drivers/gpu/drm/display/drm_dp_mst_topology.c

4155

up_req->msg.req_type);

drivers/gpu/drm/display/drm_dp_mst_topology.c

4169

drm_dp_send_up_ack_reply(mgr, mst_primary, up_req->msg.req_type,

drivers/gpu/drm/display/drm_dp_mst_topology.c

4174

if (up_req->msg.req_type == DP_CONNECTION_STATUS_NOTIFY) {

drivers/gpu/drm/display/drm_dp_mst_topology.c

4185

} else if (up_req->msg.req_type == DP_RESOURCE_STATUS_NOTIFY) {

drivers/gpu/drm/display/drm_dp_mst_topology.c

474

req->req_type = buf[idx++] & 0x7f;

drivers/gpu/drm/display/drm_dp_mst_topology.c

475

switch (req->req_type) {

drivers/gpu/drm/display/drm_dp_mst_topology.c

5848

msg.req_type = DP_REMOTE_I2C_READ;

drivers/gpu/drm/display/drm_dp_mst_topology.c

5907

msg.req_type = DP_REMOTE_I2C_WRITE;

drivers/gpu/drm/display/drm_dp_mst_topology.c

616

if (req->req_type == DP_LINK_ADDRESS) {

drivers/gpu/drm/display/drm_dp_mst_topology.c

618

P("type=%s\n", drm_dp_mst_req_type_str(req->req_type));

drivers/gpu/drm/display/drm_dp_mst_topology.c

622

P("type=%s contents:\n", drm_dp_mst_req_type_str(req->req_type));

drivers/gpu/drm/display/drm_dp_mst_topology.c

625

switch (req->req_type) {

drivers/gpu/drm/display/drm_dp_mst_topology.c

722

switch (req.req_type) {

drivers/gpu/drm/display/drm_dp_mst_topology.c

750

buf[idx++] = (rep->reply_type & 0x1) << 7 | (rep->req_type & 0x7f);

drivers/gpu/drm/radeon/radeon_acpi.c

623

atcs_input.req_type = ATCS_PCIE_LINK_SPEED;

drivers/gpu/drm/radeon/radeon_acpi.c

91

u8 req_type; /* request type */

drivers/gpu/drm/tests/drm_dp_mst_helper_test.c

226

.req_type = DP_ENUM_PATH_RESOURCES,

drivers/gpu/drm/tests/drm_dp_mst_helper_test.c

233

.req_type = DP_POWER_UP_PHY,

drivers/gpu/drm/tests/drm_dp_mst_helper_test.c

240

.req_type = DP_POWER_DOWN_PHY,

drivers/gpu/drm/tests/drm_dp_mst_helper_test.c

247

.req_type = DP_ALLOCATE_PAYLOAD,

drivers/gpu/drm/tests/drm_dp_mst_helper_test.c

255

.req_type = DP_ALLOCATE_PAYLOAD,

drivers/gpu/drm/tests/drm_dp_mst_helper_test.c

262

.req_type = DP_ALLOCATE_PAYLOAD,

drivers/gpu/drm/tests/drm_dp_mst_helper_test.c

269

.req_type = DP_ALLOCATE_PAYLOAD,

drivers/gpu/drm/tests/drm_dp_mst_helper_test.c

276

.req_type = DP_QUERY_PAYLOAD,

drivers/gpu/drm/tests/drm_dp_mst_helper_test.c

283

.req_type = DP_QUERY_PAYLOAD,

drivers/gpu/drm/tests/drm_dp_mst_helper_test.c

290

.req_type = DP_REMOTE_DPCD_READ,

drivers/gpu/drm/tests/drm_dp_mst_helper_test.c

297

.req_type = DP_REMOTE_DPCD_READ,

drivers/gpu/drm/tests/drm_dp_mst_helper_test.c

304

.req_type = DP_REMOTE_DPCD_READ,

drivers/gpu/drm/tests/drm_dp_mst_helper_test.c

311

.req_type = DP_REMOTE_DPCD_WRITE,

drivers/gpu/drm/tests/drm_dp_mst_helper_test.c

318

.req_type = DP_REMOTE_DPCD_WRITE,

drivers/gpu/drm/tests/drm_dp_mst_helper_test.c

325

.req_type = DP_REMOTE_DPCD_WRITE,

drivers/gpu/drm/tests/drm_dp_mst_helper_test.c

333

.req_type = DP_REMOTE_I2C_READ,

drivers/gpu/drm/tests/drm_dp_mst_helper_test.c

340

.req_type = DP_REMOTE_I2C_READ,

drivers/gpu/drm/tests/drm_dp_mst_helper_test.c

347

.req_type = DP_REMOTE_I2C_READ,

drivers/gpu/drm/tests/drm_dp_mst_helper_test.c

363

.req_type = DP_REMOTE_I2C_WRITE,

drivers/gpu/drm/tests/drm_dp_mst_helper_test.c

370

.req_type = DP_REMOTE_I2C_WRITE,

drivers/gpu/drm/tests/drm_dp_mst_helper_test.c

377

.req_type = DP_REMOTE_I2C_WRITE,