drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

330

CP_HQD_PQ_CONTROL, QUEUE_SIZE);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

255

CP_HQD_PQ_CONTROL, QUEUE_SIZE);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

241

CP_HQD_PQ_CONTROL, QUEUE_SIZE);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

226

CP_HQD_PQ_CONTROL, QUEUE_SIZE);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

269

CP_HQD_PQ_CONTROL, QUEUE_SIZE);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6974

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6976

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6979

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6981

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6982

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6984

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6985

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4308

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4310

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4312

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4313

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4316

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4317

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4320

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TMZ, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3179

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3181

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3183

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3184

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3186

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3187

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3190

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TMZ, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2181

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2183

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2185

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2186

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2187

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2188

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4452

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4454

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4457

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4459

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4460

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4461

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4462

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3628

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3630

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3633

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3635

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3636

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3637

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3638

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1904

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1906

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1909

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1911

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1912

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1913

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1914

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1170

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1172

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1174

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1175

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1176

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1177

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1178

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1328

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1330

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1332

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1333

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1334

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1335

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1336

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1253

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1255

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1257

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1258

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1259

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1260

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1261

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1);

drivers/gpu/drm/radeon/cik.c

4658

mqd->queue_state.cp_hqd_pq_control = RREG32(CP_HQD_PQ_CONTROL);

drivers/gpu/drm/radeon/cik.c

4673

WREG32(CP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control);