reg_wr
unsigned int reg_wr, reg_rd, data_wr;
reg_wr = AD7293_REG_VINX_SEQ;
reg_wr = AD7293_REG_ISENSEX_TSENSEX_SEQ;
reg_wr = AD7293_REG_ISENSEX_TSENSEX_SEQ;
ret = __ad7293_spi_write(st, reg_wr, data_wr);
reg->reg_wr.wr.opcode = IB_WR_REG_MR;
reg->reg_wr.mr = reg->mr;
reg->reg_wr.access = IB_ACCESS_LOCAL_WRITE;
reg->reg_wr.access |= IB_ACCESS_REMOTE_WRITE;
prev->wr.wr.next = ®->reg_wr.wr;
reg->reg_wr.wr.next = ®->wr.wr;
ctx->reg->reg_wr.wr.opcode = IB_WR_REG_MR_INTEGRITY;
ctx->reg->reg_wr.wr.wr_cqe = NULL;
ctx->reg->reg_wr.wr.num_sge = 0;
ctx->reg->reg_wr.wr.send_flags = 0;
ctx->reg->reg_wr.access = IB_ACCESS_LOCAL_WRITE;
ctx->reg->reg_wr.access |= IB_ACCESS_REMOTE_WRITE;
ctx->reg->reg_wr.mr = ctx->reg->mr;
ctx->reg->reg_wr.key = ctx->reg->mr->lkey;
reg->inv_wr.next = ®->reg_wr.wr;
ctx->reg->reg_wr.wr.next = &rdma_wr->wr;
reg->reg_wr.key = reg->mr->lkey;
first_wr = &ctx->reg[0].reg_wr.wr;
rc = bnxt_re_build_reg_wqe(reg_wr(wr), &wqe);
struct c4iw_mr *mhp = to_c4iw_mr(reg_wr(wr)->mr);
build_tpte_memreg(&wqe->fr_tpte, reg_wr(wr),
err = build_memreg(&qhp->wq.sq, wqe, reg_wr(wr),
mr = to_emr(reg_wr(send_wr)->mr);
to_erdma_access_flags(reg_wr(send_wr)->access);
regmr_sge->stag = cpu_to_le32(reg_wr(send_wr)->key);
set_frmr_seg(rc_sq_wqe, reg_wr(wr));
rc = ionic_prep_reg(qp, reg_wr(wr));
struct irdma_mr *iwmr = to_iwmr(reg_wr(ib_wr)->mr);
irdma_get_mr_access(reg_wr(ib_wr)->access,
stag_info.stag_key = reg_wr(ib_wr)->key & 0xff;
stag_info.stag_idx = reg_wr(ib_wr)->key >> 8;
stag_info.page_size = reg_wr(ib_wr)->mr->page_size;
set_reg_seg(wqe, reg_wr(wr));
const struct ib_reg_wr *wr = reg_wr(send_wr);
(*ctrl)->imm = cpu_to_be32(reg_wr(wr)->key);
return set_reg_wr(qp, reg_wr(wr), seg, size, cur_edge, true);
mr = to_mmr(reg_wr(wr)->mr);
reg_pi_wr.access = reg_wr(wr)->access;
status = ocrdma_build_reg(qp, hdr, reg_wr(wr));
rc = qedr_prepare_reg(qp, fwqe1, reg_wr(wr));
ret = set_reg_seg(wqe_hdr, reg_wr(wr));
reg_wr(wr)->mr,
reg_wr(wr)->key,
reg_wr(wr)->access);
wr->wr.reg.mr = reg_wr(ibwr)->mr;
wr->wr.reg.key = reg_wr(ibwr)->key;
wr->wr.reg.access = reg_wr(ibwr)->access;
sqe->base_mr = (uintptr_t)reg_wr(wr)->mr;
sqe->rkey = reg_wr(wr)->key;
sqe->access = reg_wr(wr)->access & IWARP_ACCESS_MASK;
tx_desc->reg_wr.wr.next = NULL;
struct ib_reg_wr reg_wr;
struct ib_reg_wr *wr = &tx_desc->reg_wr;
struct ib_reg_wr *wr = &tx_desc->reg_wr;
else if (tx_desc->reg_wr.wr.next)
first_wr = &tx_desc->reg_wr.wr;
struct ib_send_wr *reg_wr = NULL;
reg_wr = &rwr[mri].wr;
err = rtrs_iu_post_send(&con->c, tx_iu, tx_sz, reg_wr);
DEFINE_EVENT(dev_reg_evt, reg_wr,
memset(&req->reg_wr, 0, sizeof(req->reg_wr));
req->reg_wr.wr.opcode = IB_WR_REG_MR;
req->reg_wr.wr.wr_cqe = &req->reg_cqe;
req->reg_wr.wr.num_sge = 0;
req->reg_wr.mr = req->mr;
req->reg_wr.key = req->mr->rkey;
req->reg_wr.access = IB_ACCESS_LOCAL_WRITE |
struct ib_reg_wr *wr = &req->reg_wr;
req->mr ? &req->reg_wr.wr : NULL);
struct ib_reg_wr reg_wr;
struct ib_reg_wr *reg_wr;
reg_wr = &mr->wr;
reg_wr->wr.opcode = IB_WR_REG_MR;
reg_wr->wr.wr_cqe = &mr->cqe;
reg_wr->wr.num_sge = 0;
reg_wr->wr.send_flags = IB_SEND_SIGNALED;
reg_wr->mr = mr->mr;
reg_wr->key = mr->mr->rkey;
reg_wr->access = writing ?
ret = ib_post_send(sc->ib.qp, ®_wr->wr, NULL);
ret, SMBDIRECT_DEBUG_ERR_PTR(ret), reg_wr->key);
struct ib_reg_wr reg_wr;
struct ib_reg_wr reg_wr;
struct ib_reg_wr reg_wr;
memset(®_wr, 0, sizeof(reg_wr));
reg_wr.wr.wr_id = (unsigned long)(void *)ibmr;
reg_wr.wr.opcode = IB_WR_REG_MR;
reg_wr.wr.num_sge = 0;
reg_wr.mr = frmr->mr;
reg_wr.key = frmr->mr->rkey;
reg_wr.access = IB_ACCESS_LOCAL_WRITE |
reg_wr.wr.send_flags = IB_SEND_SIGNALED;
ret = ib_post_send(ibmr->ic->i_cm_id->qp, ®_wr.wr, NULL);
struct ib_reg_wr *reg_wr;
reg_wr = &mr->mr_regwr;
reg_wr->mr = ibmr;
reg_wr->key = ibmr->rkey;
reg_wr->access = writing ?
struct ib_reg_wr *reg_wr;
reg_wr = &mr->mr_regwr;
reg_wr->mr = ibmr;
reg_wr->key = ibmr->rkey;
reg_wr->access = IB_ACCESS_REMOTE_WRITE | IB_ACCESS_LOCAL_WRITE;