arch/mips/cavium-octeon/csrc-octeon.c

43

union cvmx_mio_rst_boot rst_boot;

arch/mips/cavium-octeon/csrc-octeon.c

45

rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);

arch/mips/cavium-octeon/csrc-octeon.c

46

rdiv = rst_boot.s.c_mul; /* CPU clock */

arch/mips/cavium-octeon/csrc-octeon.c

47

sdiv = rst_boot.s.pnr_mul; /* I/O clock */

arch/mips/cavium-octeon/csrc-octeon.c

50

union cvmx_rst_boot rst_boot;

arch/mips/cavium-octeon/csrc-octeon.c

52

rst_boot.u64 = cvmx_read_csr(CVMX_RST_BOOT);

arch/mips/cavium-octeon/csrc-octeon.c

53

rdiv = rst_boot.s.c_mul; /* CPU clock */

arch/mips/cavium-octeon/csrc-octeon.c

54

sdiv = rst_boot.s.pnr_mul; /* I/O clock */

arch/mips/cavium-octeon/setup.c

717

union cvmx_mio_rst_boot rst_boot;

arch/mips/cavium-octeon/setup.c

718

rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);

arch/mips/cavium-octeon/setup.c

719

octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul;

arch/mips/cavium-octeon/setup.c

722

union cvmx_rst_boot rst_boot;

arch/mips/cavium-octeon/setup.c

723

rst_boot.u64 = cvmx_read_csr(CVMX_RST_BOOT);

arch/mips/cavium-octeon/setup.c

724

octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul;

drivers/crypto/cavium/nitrox/nitrox_hal.c

611

union rst_boot rst_boot;

drivers/crypto/cavium/nitrox/nitrox_hal.c

619

rst_boot.value = nitrox_read_csr(ndev, offset);

drivers/crypto/cavium/nitrox/nitrox_hal.c

620

ndev->hw.freq = (rst_boot.pnr_mul + 3) * PLL_REF_CLK;