reg_rmw
assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
assign_register(reg_rmw(ctxt, reg), val, ctxt->op_bytes);
ctxt->src.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
*reg_rmw(ctxt, VCPU_REGS_RSI) &= (u32)-1;
*reg_rmw(ctxt, VCPU_REGS_RDI) &= (u32)-1;
ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
*reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
*reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
ulong *preg = reg_rmw(ctxt, reg);
masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
p = reg_rmw(ctxt, modrm_reg);
reg_rmw(serdes_regs + cfg_phyb_1p25g_156p25mhz_cmu0[i].ofs,
reg_rmw(serdes_regs + cfg_phyb_10p3125g_156p25mhz_cmu1[i].ofs,
reg_rmw(serdes_regs +
reg_rmw(serdes_regs + (0x200 * lane) + 0x0380,
reg_rmw(serdes_regs + (0x200 * lane) + 0x03c0,
reg_rmw(serdes_regs + cfg_phyb_10p3125g_comlane[i].ofs,
reg_rmw(serdes_regs + 0x0a00, 0x0000001f, 0x000000ff);
reg_rmw(serdes_regs + 0x0008, ((select << 5) + ofs) << 24,
reg_rmw(serdes_regs + 0x00fc, ((select << 8) + ofs) << 16, ~0xf800ffff);
reg_rmw(sig_detect_reg, VAL_SH(2, 1), MASK_WID_SH(2, 1));
reg_rmw(sig_detect_reg, VAL_SH(0, 1), MASK_WID_SH(2, 1));
reg_rmw(sig_detect_reg, VAL_SH(3, 1),
reg_rmw(pcsr_base + 0x08 + (i * 0x80), VAL_SH(0x19, 0),
reg_rmw(pcsr_base + 0x08 + (i * 0x80), VAL_SH(0x00, 0),
reg_rmw(serdes_regs + cfg_cm_c1_c2[i].ofs + (0x200 * lane),
reg_rmw(serdes_regs + PCSR_CPU_CTRL_OFFSET, POR_EN, POR_EN);
reg_rmw(serdes_regs + PCSR_CPU_CTRL_OFFSET, 0, POR_EN);