reg_clear
reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT |
reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
reg_clear(priv, REG_TX4, TX4_PD_RAM);
reg_clear(priv, REG_TX33, TX33_HDMI);
reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ);
reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR |
reg_clear(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_CSC);
reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
reg_clear(priv, REG_DIP_IF_FLAGS, bit);
reg_clear(priv, REG_DIP_IF_FLAGS, DIP_IF_FLAGS_IF1);
reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
reg_clear(HC_CONTROL, HC_CONTROL_BUS_ENABLE);
reg_clear(HC_CONTROL, HC_CONTROL_HOT_JOIN_CTRL);
reg_clear(HC_CONTROL, HC_CONTROL_PIO_MODE);
ret = reg_clear(client, MT9M001_READ_OPTIONS2, 0x8000);
ret = reg_clear(RESET, MT9M111_RESET_RESET_MODE
return reg_clear(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOEXPO_EN);
return reg_clear(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOWHITEBAL_EN);
ret = reg_clear(RESET, MT9M111_RESET_CHIP_ENABLE);
reg_clear(dcmi->regs, DCMI_CR, CR_CAPTURE);
reg_clear(dcmi->regs, DCMI_IER, IT_FRAME | IT_OVR | IT_ERR);
reg_clear(dcmi->regs, DCMI_CR, CR_ENABLE);
reg_clear(vcap, DCMIPP_CMIER, DCMIPP_CMIER_P0ALL);
reg_clear(vcap, DCMIPP_P0FCTCR, DCMIPP_P0FCTCR_CPTREQ);
reg_clear(vcap, DCMIPP_P0FSCR, DCMIPP_P0FSCR_PIPEN);
reg_clear(vcap, DCMIPP_P0FCTCR, DCMIPP_P0FCTCR_CPTREQ);
reg_clear(byteproc, DCMIPP_P0PPCR, DCMIPP_P0PPCR_BSM_MASK);
reg_clear(byteproc, DCMIPP_P0PPCR, DCMIPP_P0PPCR_LSM);
reg_clear(inp, DCMIPP_P0FSCR,
reg_clear(inp, DCMIPP_PRCR, DCMIPP_PRCR_ENABLE);
u32 irq_status, reg_set, reg_clear;
reg_clear = reg_set;
reg_clear &= ~USBINT_CFG1_USBDRD_PME_GEN_U2_INTR_CLR;
reg_clear &= ~USBINT_CFG1_USBDRD_PME_GEN_U3_INTR_CLR;
google->usbint_cfg_offset + USBINT_CFG1_OFFSET, reg_clear);