drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

3786

u32 val, reg, reg_bit;

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

3792

reg_bit = HCLGE_IMP_RESET_BIT;

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

3796

reg_bit = HCLGE_GLOBAL_RESET_BIT;

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

3800

reg_bit = HCLGE_FUN_RST_ING_B;

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

3810

while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) {

drivers/net/ipa/gsi.c

1970

iowrite32(reg_bit(reg, INTYPE), gsi->virt + reg_offset(reg));

drivers/net/ipa/gsi.c

2075

if (!(val & reg_bit(reg, ENABLED))) {

drivers/net/ipa/gsi.c

727

val |= reg_bit(reg, EV_INTYPE);

drivers/net/ipa/gsi.c

840

val |= reg_bit(reg, CHTYPE_DIR);

drivers/net/ipa/gsi.c

875

val |= reg_bit(reg, USE_DB_ENG);

drivers/net/ipa/gsi.c

883

val |= reg_bit(reg, USE_ESCAPE_BUF_ONLY);

drivers/net/ipa/gsi.c

889

val |= reg_bit(reg, DB_IN_BYTES);

drivers/net/ipa/ipa_endpoint.c

1025

val |= reg_bit(reg, SW_EOF_ACTIVE);

drivers/net/ipa/ipa_endpoint.c

1136

val = enable ? reg_bit(reg, HOL_BLOCK_EN) : 0;

drivers/net/ipa/ipa_endpoint.c

1281

val |= reg_bit(reg, STATUS_EN);

drivers/net/ipa/ipa_endpoint.c

1647

val |= reg_bit(reg, ROUTE_DEF_HDR_TABLE);

drivers/net/ipa/ipa_endpoint.c

1650

val |= reg_bit(reg, ROUTE_DEF_RETAIN_HDR);

drivers/net/ipa/ipa_endpoint.c

470

mask = reg_bit(reg, field_id);

drivers/net/ipa/ipa_endpoint.c

814

val |= reg_bit(reg, HDR_OFST_PKT_SIZE_VALID);

drivers/net/ipa/ipa_endpoint.c

818

val |= reg_bit(reg, HDR_OFST_METADATA_VALID);

drivers/net/ipa/ipa_endpoint.c

840

val |= reg_bit(reg, HDR_ENDIANNESS); /* big endian */

drivers/net/ipa/ipa_endpoint.c

850

val |= reg_bit(reg, HDR_TOTAL_LEN_OR_PAD_VALID);

drivers/net/ipa/ipa_endpoint.c

852

val |= reg_bit(reg, HDR_PAYLOAD_LEN_INC_PADDING);

drivers/net/ipa/ipa_main.c

226

val &= ~reg_bit(reg, PA_MASK_EN);

drivers/net/ipa/ipa_main.c

247

val = reg_bit(reg, CLKON_MISC);

drivers/net/ipa/ipa_main.c

250

val = reg_bit(reg, CLKON_GLOBAL);

drivers/net/ipa/ipa_main.c

251

val |= reg_bit(reg, GLOBAL_2X_CLK);

drivers/net/ipa/ipa_main.c

274

val &= ~reg_bit(reg, IPA_QMB_SELECT_CONS_EN);

drivers/net/ipa/ipa_main.c

275

val &= ~reg_bit(reg, IPA_QMB_SELECT_PROD_EN);

drivers/net/ipa/ipa_main.c

276

val &= ~reg_bit(reg, IPA_QMB_SELECT_GLOBAL_EN);

drivers/net/ipa/ipa_main.c

278

val |= reg_bit(reg, GSI_MULTI_AXI_MASTERS_DIS);

drivers/net/ipa/ipa_main.c

283

val |= reg_bit(reg, GSI_MULTI_INORDER_RD_DIS);

drivers/net/ipa/ipa_main.c

284

val |= reg_bit(reg, GSI_MULTI_INORDER_WR_DIS);

drivers/net/ipa/ipa_main.c

374

val |= reg_bit(reg, DPL_TIMESTAMP_SEL);

drivers/net/ipa/ipa_main.c

404

val |= reg_bit(reg, DIV_ENABLE);

drivers/net/ipa/ipa_main.c

465

val |= reg_bit(reg, CONST_NON_IDLE_ENABLE);

drivers/net/ipa/ipa_table.c

367

val = reg_bit(reg, IPV6_ROUTER_HASH);

drivers/net/ipa/ipa_table.c

368

val |= reg_bit(reg, IPV6_FILTER_HASH);

drivers/net/ipa/ipa_table.c

369

val |= reg_bit(reg, IPV4_ROUTER_HASH);

drivers/net/ipa/ipa_table.c

370

val |= reg_bit(reg, IPV4_FILTER_HASH);

drivers/net/ipa/ipa_table.c

375

val = reg_bit(reg, ROUTER_CACHE);

drivers/net/ipa/ipa_table.c

376

val |= reg_bit(reg, FILTER_CACHE);

drivers/net/ipa/ipa_uc.c

245

val = reg_bit(reg, UC_INTR);

drivers/pci/controller/pcie-rzg3s-host.c

567

u8 reg_bit = bit % RZG3S_PCI_MSI_INT_PER_REG;

drivers/pci/controller/pcie-rzg3s-host.c

571

writel_relaxed(BIT(reg_bit),

drivers/pci/controller/pcie-rzg3s-host.c

583

u8 reg_bit = d->hwirq % RZG3S_PCI_MSI_INT_PER_REG;

drivers/pci/controller/pcie-rzg3s-host.c

586

writel_relaxed(BIT(reg_bit), host->axi + RZG3S_PCI_MSIRS(reg_id));

drivers/pci/controller/pcie-rzg3s-host.c

593

u8 reg_bit = d->hwirq % RZG3S_PCI_MSI_INT_PER_REG;

drivers/pci/controller/pcie-rzg3s-host.c

598

rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_MSIRM(reg_id), BIT(reg_bit),

drivers/pci/controller/pcie-rzg3s-host.c

599

BIT(reg_bit));

drivers/pci/controller/pcie-rzg3s-host.c

606

u8 reg_bit = d->hwirq % RZG3S_PCI_MSI_INT_PER_REG;

drivers/pci/controller/pcie-rzg3s-host.c

611

rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_MSIRM(reg_id), BIT(reg_bit),

drivers/perf/arm_cspmu/arm_cspmu.c

756

u32 reg_id, reg_bit, inten_off, cnten_off;

drivers/perf/arm_cspmu/arm_cspmu.c

759

reg_bit = COUNTER_TO_SET_CLR_BIT(idx);

drivers/perf/arm_cspmu/arm_cspmu.c

764

writel(BIT(reg_bit), cspmu->base0 + inten_off);

drivers/perf/arm_cspmu/arm_cspmu.c

765

writel(BIT(reg_bit), cspmu->base0 + cnten_off);

drivers/perf/arm_cspmu/arm_cspmu.c

770

u32 reg_id, reg_bit, inten_off, cnten_off;

drivers/perf/arm_cspmu/arm_cspmu.c

773

reg_bit = COUNTER_TO_SET_CLR_BIT(idx);

drivers/perf/arm_cspmu/arm_cspmu.c

778

writel(BIT(reg_bit), cspmu->base0 + cnten_off);

drivers/perf/arm_cspmu/arm_cspmu.c

779

writel(BIT(reg_bit), cspmu->base0 + inten_off);