Symbol: reg_ctl
drivers/clk/nuvoton/clk-ma35d1-pll.c
104
if (reg_ctl[1] & PLL_CTL1_BP)
drivers/clk/nuvoton/clk-ma35d1-pll.c
107
n = FIELD_GET(PLL_CTL0_FBDIV, reg_ctl[0]);
drivers/clk/nuvoton/clk-ma35d1-pll.c
108
m = FIELD_GET(PLL_CTL0_INDIV, reg_ctl[0]);
drivers/clk/nuvoton/clk-ma35d1-pll.c
109
p = FIELD_GET(PLL_CTL1_OUTDIV, reg_ctl[1]);
drivers/clk/nuvoton/clk-ma35d1-pll.c
115
x = FIELD_GET(PLL_CTL1_FRAC, reg_ctl[1]);
drivers/clk/nuvoton/clk-ma35d1-pll.c
124
unsigned long parent_rate, u32 *reg_ctl,
drivers/clk/nuvoton/clk-ma35d1-pll.c
169
reg_ctl[0] = FIELD_PREP(PLL_CTL0_INDIV, m) |
drivers/clk/nuvoton/clk-ma35d1-pll.c
171
reg_ctl[1] = FIELD_PREP(PLL_CTL1_OUTDIV, p);
drivers/clk/nuvoton/clk-ma35d1-pll.c
189
u32 reg_ctl[3] = { 0 };
drivers/clk/nuvoton/clk-ma35d1-pll.c
196
ret = ma35d1_pll_find_closest(pll, rate, parent_rate, reg_ctl, &pll_freq);
drivers/clk/nuvoton/clk-ma35d1-pll.c
202
reg_ctl[0] |= FIELD_PREP(PLL_CTL0_MODE, PLL_MODE_INT);
drivers/clk/nuvoton/clk-ma35d1-pll.c
205
reg_ctl[0] |= FIELD_PREP(PLL_CTL0_MODE, PLL_MODE_FRAC);
drivers/clk/nuvoton/clk-ma35d1-pll.c
208
reg_ctl[0] |= FIELD_PREP(PLL_CTL0_MODE, PLL_MODE_SS) |
drivers/clk/nuvoton/clk-ma35d1-pll.c
210
reg_ctl[2] = FIELD_PREP(PLL_CTL2_SLOPE, PLL_SLOPE);
drivers/clk/nuvoton/clk-ma35d1-pll.c
213
reg_ctl[1] |= PLL_CTL1_PD;
drivers/clk/nuvoton/clk-ma35d1-pll.c
215
writel_relaxed(reg_ctl[0], pll->ctl0_base);
drivers/clk/nuvoton/clk-ma35d1-pll.c
216
writel_relaxed(reg_ctl[1], pll->ctl1_base);
drivers/clk/nuvoton/clk-ma35d1-pll.c
217
writel_relaxed(reg_ctl[2], pll->ctl2_base);
drivers/clk/nuvoton/clk-ma35d1-pll.c
224
u32 reg_ctl[3];
drivers/clk/nuvoton/clk-ma35d1-pll.c
232
reg_ctl[0] = readl_relaxed(pll->ctl0_base);
drivers/clk/nuvoton/clk-ma35d1-pll.c
233
pll_freq = ma35d1_calc_smic_pll_freq(reg_ctl[0], parent_rate);
drivers/clk/nuvoton/clk-ma35d1-pll.c
239
reg_ctl[0] = readl_relaxed(pll->ctl0_base);
drivers/clk/nuvoton/clk-ma35d1-pll.c
240
reg_ctl[1] = readl_relaxed(pll->ctl1_base);
drivers/clk/nuvoton/clk-ma35d1-pll.c
241
pll_freq = ma35d1_calc_pll_freq(pll->mode, reg_ctl, parent_rate);
drivers/clk/nuvoton/clk-ma35d1-pll.c
251
u32 reg_ctl[3] = { 0 };
drivers/clk/nuvoton/clk-ma35d1-pll.c
259
reg_ctl, &pll_freq);
drivers/clk/nuvoton/clk-ma35d1-pll.c
265
reg_ctl[0] = readl_relaxed(pll->ctl0_base);
drivers/clk/nuvoton/clk-ma35d1-pll.c
266
pll_freq = ma35d1_calc_smic_pll_freq(reg_ctl[0], req->best_parent_rate);
drivers/clk/nuvoton/clk-ma35d1-pll.c
274
reg_ctl[0] = readl_relaxed(pll->ctl0_base);
drivers/clk/nuvoton/clk-ma35d1-pll.c
275
reg_ctl[1] = readl_relaxed(pll->ctl1_base);
drivers/clk/nuvoton/clk-ma35d1-pll.c
276
pll_freq = ma35d1_calc_pll_freq(pll->mode, reg_ctl, req->best_parent_rate);
drivers/clk/nuvoton/clk-ma35d1-pll.c
99
static unsigned long ma35d1_calc_pll_freq(u8 mode, u32 *reg_ctl, unsigned long parent_rate)
drivers/clocksource/timer-econet-en751221.c
103
reg = ioread32(reg_ctl(cpu)) | ctl_bit_enabled(cpu);
drivers/clocksource/timer-econet-en751221.c
104
iowrite32(reg, reg_ctl(cpu));
drivers/clocksource/timer-econet-en751221.c
62
return ioread32(reg_ctl(cpu_id)) & ctl_bit_pending(cpu_id);
drivers/gpu/drm/i915/display/intel_dmc.c
571
intel_reg_t reg_ctl, u32 *data_ctl,
drivers/gpu/drm/i915/display/intel_dmc.c
574
if (!is_dmc_evt_ctl_reg(display, dmc_id, reg_ctl))
drivers/gpu/drm/i915/display/intel_dmc.c
581
if (intel_reg_offset(reg_ctl) - intel_reg_offset(DMC_EVT_CTL(display, dmc_id, 0)) !=
drivers/gpu/drm/i915/display/intel_dmc.c
590
is_event_handler(display, dmc_id, MAINDMC_EVENT_VBLANK_A, reg_ctl, *data_ctl)) {
drivers/gpu/drm/i915/display/intel_dmc.c
604
is_event_handler(display, dmc_id, MAINDMC_EVENT_VBLANK_A, reg_ctl, *data_ctl)) {
drivers/gpu/drm/xe/xe_force_wake.c
101
xe_mmio_write32(&gt->mmio, domain->reg_ctl, domain->mask | (wake ? domain->val : 0));
drivers/gpu/drm/xe/xe_force_wake.c
37
domain->reg_ctl = reg;
drivers/gpu/drm/xe/xe_force_wake.h
28
(domain__)->reg_ctl.addr)
drivers/gpu/drm/xe/xe_force_wake_types.h
76
struct xe_reg reg_ctl;
drivers/gpu/drm/xe/xe_gt_idle.c
186
xe_mmio_read32(&gt->mmio, domain->reg_ctl));