drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1096

WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1286

WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

65

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1343

WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

59

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

976

WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1009

WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1199

WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

65

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

49

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

766

WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

927

WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1097

WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, ring->gpu_addr);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

52

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

752

WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, lower_32_bits(ring->gpu_addr));

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c

648

WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, lower_32_bits(ring->gpu_addr));

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c

801

WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, ring->gpu_addr);