drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1076

VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1175

WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1638

tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1640

WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1238

WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_LMI_CTRL2), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1455

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1457

WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2, tmp);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

953

VCN, 0, regUVD_LMI_CTRL2), tmp, 0, indirect);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1087

WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1301

tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1303

WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

992

VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

1032

tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

1034

WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

749

VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

841

WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1007

WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_LMI_CTRL2), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1202

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1204

WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2, tmp);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

729

VCN, 0, regUVD_LMI_CTRL2), tmp, 0, indirect);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c

625

VCN, 0, regUVD_LMI_CTRL2), tmp, 0, indirect);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c

711

WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_LMI_CTRL2), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c

896

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c

898

WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2, tmp);