rsci_serial_out
rsci_serial_out(port, CFCLR, CFCLR_RDRFC);
rsci_serial_out(port, FFCLR, FFCLR_DRC);
rsci_serial_out(port, CCR0, ctrl);
rsci_serial_out(port, CCR1, rsci_serial_in(port, CCR1) |
rsci_serial_out(port, FCR, fcr);
rsci_serial_out(port, CCR0, ccr0_val);
rsci_serial_out(port, CCR3, ccr3_val);
rsci_serial_out(port, CCR2, ccr2_val);
rsci_serial_out(port, CCR1, ccr1_val);
rsci_serial_out(port, CCR4, ccr4_val);
rsci_serial_out(port, FCR, ctrl);
rsci_serial_out(port, CFCLR, CFCLR_CLRFLAG);
rsci_serial_out(port, FFCLR, FFCLR_DRC);
rsci_serial_out(port, CCR0, ccr0_val);
rsci_serial_out(port, CCR1, rsci_serial_in(port, CCR1) | CCR1_SPLP);
rsci_serial_out(port, CFCLR, mask);
rsci_serial_out(port, CCR0, ctrl);
rsci_serial_out(port, CCR0, ctrl);
rsci_serial_out(port, CCR0, ctrl);
rsci_serial_out(port, CCR0, ctrl);
rsci_serial_out(port, TDR, c);
rsci_serial_out(port, CCR0, ctrl);
rsci_serial_out(port, CCR1, ccr1_val);
rsci_serial_out(port, CCR0, ccr0_val);
rsci_serial_out(port, TDR, c);
rsci_serial_out(port, CCR0, ctrl_temp);
rsci_serial_out(port, CCR0, ctrl & ~CCR0_TE);
rsci_serial_out(port, CCR0, ctrl);
rsci_serial_out(port, CCR0, 0);
.write_reg = rsci_serial_out,