drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1165

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1167

WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1198

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1200

WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1260

data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1262

WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1835

data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1837

WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1885

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1887

WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1897

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1899

WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

828

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

830

WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

871

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

873

WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

920

data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

922

WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

771

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

773

WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

794

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

796

WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c

1174

data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c

1176

WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c

1224

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c

1226

WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c

1236

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c

1238

WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);