drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1165

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1167

WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1198

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1200

WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1260

data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1262

WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1834

data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1836

WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1884

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1886

WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1896

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1898

WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

828

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

830

WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

871

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

873

WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

920

data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

922

WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

771

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

773

WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

794

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

796

WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c

1173

data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c

1175

WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c

1223

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c

1225

WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c

1235

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c

1237

WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);