Symbol: rreg_t
drivers/atm/iphase.h
717
rreg_t mode_reg_0; /* Mode register 0 */
drivers/atm/iphase.h
718
rreg_t protocol_id; /* Protocol ID */
drivers/atm/iphase.h
719
rreg_t mask_reg; /* Mask Register */
drivers/atm/iphase.h
720
rreg_t intr_status_reg;/* Interrupt status register */
drivers/atm/iphase.h
721
rreg_t drp_pkt_cntr; /* Dropped packet cntr (clear on read) */
drivers/atm/iphase.h
722
rreg_t err_cntr; /* Error Counter (cleared on read) */
drivers/atm/iphase.h
724
rreg_t raw_base_adr; /* Base addr for raw cell Q */
drivers/atm/iphase.h
726
rreg_t cell_ctr0; /* Cell Counter 0 (cleared when read) */
drivers/atm/iphase.h
727
rreg_t cell_ctr1; /* Cell Counter 1 (cleared when read) */
drivers/atm/iphase.h
729
rreg_t cmd_reg; /* Command register */
drivers/atm/iphase.h
730
rreg_t desc_base; /* Base address for description table */
drivers/atm/iphase.h
731
rreg_t vc_lkup_base; /* Base address for VC lookup table */
drivers/atm/iphase.h
732
rreg_t reass_base; /* Base address for reassembler table */
drivers/atm/iphase.h
733
rreg_t queue_base; /* Base address for Communication queue */
drivers/atm/iphase.h
735
rreg_t pkt_tm_cnt; /* Packet Timeout and count register */
drivers/atm/iphase.h
736
rreg_t tmout_range; /* Range of reassembley IDs for timeout */
drivers/atm/iphase.h
737
rreg_t intrvl_cntr; /* Packet aging interval counter */
drivers/atm/iphase.h
738
rreg_t tmout_indx; /* index of pkt being tested for aging */
drivers/atm/iphase.h
740
rreg_t vp_lkup_base; /* Base address for VP lookup table */
drivers/atm/iphase.h
741
rreg_t vp_filter; /* VP filter register */
drivers/atm/iphase.h
742
rreg_t abr_lkup_base; /* Base address of ABR VC Table */
drivers/atm/iphase.h
744
rreg_t fdq_st_adr; /* Free desc queue start address */
drivers/atm/iphase.h
745
rreg_t fdq_ed_adr; /* Free desc queue end address */
drivers/atm/iphase.h
746
rreg_t fdq_rd_ptr; /* Free desc queue read pointer */
drivers/atm/iphase.h
747
rreg_t fdq_wr_ptr; /* Free desc queue write pointer */
drivers/atm/iphase.h
748
rreg_t pcq_st_adr; /* Packet Complete queue start address */
drivers/atm/iphase.h
749
rreg_t pcq_ed_adr; /* Packet Complete queue end address */
drivers/atm/iphase.h
750
rreg_t pcq_rd_ptr; /* Packet Complete queue read pointer */
drivers/atm/iphase.h
751
rreg_t pcq_wr_ptr; /* Packet Complete queue write pointer */
drivers/atm/iphase.h
752
rreg_t excp_st_adr; /* Exception queue start address */
drivers/atm/iphase.h
753
rreg_t excp_ed_adr; /* Exception queue end address */
drivers/atm/iphase.h
754
rreg_t excp_rd_ptr; /* Exception queue read pointer */
drivers/atm/iphase.h
755
rreg_t excp_wr_ptr; /* Exception queue write pointer */
drivers/atm/iphase.h
757
rreg_t raw_st_adr; /* Raw Cell start address */
drivers/atm/iphase.h
758
rreg_t raw_ed_adr; /* Raw Cell end address */
drivers/atm/iphase.h
759
rreg_t raw_rd_ptr; /* Raw Cell read pointer */
drivers/atm/iphase.h
760
rreg_t raw_wr_ptr; /* Raw Cell write pointer */
drivers/atm/iphase.h
761
rreg_t state_reg; /* State Register */
drivers/atm/iphase.h
763
rreg_t buf_size; /* Buffer size */
drivers/atm/iphase.h
765
rreg_t xtra_rm_offset; /* Offset of the additional turnaround RM */
drivers/atm/iphase.h
767
rreg_t drp_pkt_cntr_nc;/* Dropped Packet cntr, Not clear on rd */
drivers/atm/iphase.h
768
rreg_t err_cntr_nc; /* Error Counter, Not clear on read */
drivers/atm/iphase.h
770
rreg_t cell_ctr0_nc; /* Cell Counter 0, Not clear on read */
drivers/atm/iphase.h
771
rreg_t cell_ctr1_nc; /* Cell Counter 1, Not clear on read */