rq_cfg
u64 rq_cfg;
rq_cfg = nicvf_queue_reg_read(nic, NIC_QSET_RQ_GEN_CFG, 0);
rq_cfg |= (1ULL << 25);
rq_cfg &= ~(1ULL << 25);
nicvf_queue_reg_write(nic, NIC_QSET_RQ_GEN_CFG, 0, rq_cfg);
NIC_QSET_RQ_GEN_CFG, 0, rq_cfg);
struct rq_cfg rq_cfg;
memset(&rq_cfg, 0, sizeof(struct rq_cfg));
rq_cfg.ena = 1;
rq_cfg.tcp_ena = 0;
nicvf_queue_reg_write(nic, NIC_QSET_RQ_0_7_CFG, qidx, *(u64 *)&rq_cfg);
struct sli4_cmd_rq_cfg rq_cfg[SLI4_CMD_REG_FCFI_NUM_RQ_CFG];
rq_cfg[i].rq_id = cpu_to_le16(0xffff);
rq_cfg[i].r_ctl_mask = (u8)hw->config.filter_def[i];
rq_cfg[i].r_ctl_match = (u8)(hw->config.filter_def[i] >> 8);
rq_cfg[i].type_mask = (u8)(hw->config.filter_def[i] >> 16);
rq_cfg[i].type_match = (u8)(hw->config.filter_def[i] >> 24);
rq_cfg[i].rq_id = cpu_to_le16(rq->hdr->id);
if (!sli_cmd_reg_fcfi(&hw->sli, buf, 0, rq_cfg))
struct sli4_cmd_rq_cfg *rq_cfg)
reg_fcfi->rqid0 = rq_cfg[0].rq_id;
reg_fcfi->rqid1 = rq_cfg[1].rq_id;
reg_fcfi->rqid2 = rq_cfg[2].rq_id;
reg_fcfi->rqid3 = rq_cfg[3].rq_id;
reg_fcfi->rq_cfg[i].r_ctl_mask = rq_cfg[i].r_ctl_mask;
reg_fcfi->rq_cfg[i].r_ctl_match = rq_cfg[i].r_ctl_match;
reg_fcfi->rq_cfg[i].type_mask = rq_cfg[i].type_mask;
reg_fcfi->rq_cfg[i].type_match = rq_cfg[i].type_match;
struct sli4_cmd_rq_cfg *rq_cfg)
reg_fcfi_mrq->rq_cfg[i].r_ctl_mask = rq_cfg[i].r_ctl_mask;
reg_fcfi_mrq->rq_cfg[i].r_ctl_match = rq_cfg[i].r_ctl_match;
reg_fcfi_mrq->rq_cfg[i].type_mask = rq_cfg[i].type_mask;
reg_fcfi_mrq->rq_cfg[i].type_match = rq_cfg[i].type_match;
reg_fcfi_mrq->rqid3 = rq_cfg[i].rq_id;
reg_fcfi_mrq->rqid2 = rq_cfg[i].rq_id;
reg_fcfi_mrq->rqid1 = rq_cfg[i].rq_id;
reg_fcfi_mrq->rqid0 = rq_cfg[i].rq_id;
rq_cfg[SLI4_CMD_REG_FCFI_NUM_RQ_CFG];
rq_cfg[SLI4_CMD_REG_FCFI_MRQ_NUM_RQ_CFG];
struct sli4_cmd_rq_cfg *rq_cfg);
struct sli4_cmd_rq_cfg *rq_cfg);