drivers/gpu/drm/imagination/pvr_cccb.c

152

struct rogue_fwif_ccb_cmd_header cmd_header = {

drivers/gpu/drm/imagination/pvr_cccb.c

183

struct rogue_fwif_ccb_cmd_header pad_cmd = {

drivers/gpu/drm/imagination/pvr_cccb.h

13

#define PADDING_COMMAND_SIZE sizeof(struct rogue_fwif_ccb_cmd_header)

drivers/gpu/drm/imagination/pvr_cccb.h

84

return sizeof(struct rogue_fwif_ccb_cmd_header) + ALIGN(cmd_size, 8);

drivers/gpu/drm/imagination/pvr_rogue_fwif_check.h

297

OFFSET_CHECK(struct rogue_fwif_ccb_cmd_header, cmd_type, 0);

drivers/gpu/drm/imagination/pvr_rogue_fwif_check.h

298

OFFSET_CHECK(struct rogue_fwif_ccb_cmd_header, cmd_size, 4);

drivers/gpu/drm/imagination/pvr_rogue_fwif_check.h

299

OFFSET_CHECK(struct rogue_fwif_ccb_cmd_header, ext_job_ref, 8);

drivers/gpu/drm/imagination/pvr_rogue_fwif_check.h

300

OFFSET_CHECK(struct rogue_fwif_ccb_cmd_header, int_job_ref, 12);

drivers/gpu/drm/imagination/pvr_rogue_fwif_check.h

301

OFFSET_CHECK(struct rogue_fwif_ccb_cmd_header, work_est_kick_data, 16);

drivers/gpu/drm/imagination/pvr_rogue_fwif_check.h

302

SIZE_CHECK(struct rogue_fwif_ccb_cmd_header, 40);