rockchip_combphy_updatel
rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK, val, RK3568_PHYREG6);
rockchip_combphy_updatel(priv, RK3568_PHYREG15_SSC_CNT_MASK,
rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK,
rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK,
rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val,
rockchip_combphy_updatel(priv, RK3576_PHYREG10_SSC_PCM_MASK,
rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK,
rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32);
rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, val, RK3568_PHYREG33);
rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK,
rockchip_combphy_updatel(priv, RK3568_PHYREG15_SSC_CNT_MASK,
rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK,
rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val,
rockchip_combphy_updatel(priv, RK3568_PHYREG13_RESISTER_MASK, val,
rockchip_combphy_updatel(priv, RK3528_PHYREG6_SSC_DIR, val, RK3528_PHYREG6);
rockchip_combphy_updatel(priv, RK3528_PHYREG80_CTLE_EN, RK3528_PHYREG80_CTLE_EN,
rockchip_combphy_updatel(priv, RK3528_PHYREG81_SLEW_RATE_CTRL, val,
rockchip_combphy_updatel(priv, RK3528_PHYREG81_CDR_PHASE_PATH_GAIN_2X,
rockchip_combphy_updatel(priv, RK3528_PHYREG83_RX_SQUELCH, val, RK3528_PHYREG83);
rockchip_combphy_updatel(priv, RK3528_PHYREG40_SSC_CNT, val,
rockchip_combphy_updatel(priv, RK3528_PHYREG86_RTERM_DET_CLK_EN,
rockchip_combphy_updatel(priv, RK3528_PHYREG5_GATE_TX_PCK_SEL,
rockchip_combphy_updatel(priv, RK3528_PHYREG6_PLL_KVCO, val,
rockchip_combphy_updatel(priv,
rockchip_combphy_updatel(priv, RK3528_PHYREG6_PLL_KVCO, val,
rockchip_combphy_updatel(priv, RK3528_PHYREG40_SSC_EN,
rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32);
rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val,
rockchip_combphy_updatel(priv, RK3568_PHYREG15_CTLE_EN,
rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK,
rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK, val, RK3568_PHYREG6);
rockchip_combphy_updatel(priv, RK3568_PHYREG15_SSC_CNT_MASK,
rockchip_combphy_updatel(priv, RK3568_PHYREG30_GATE_TX_PCK_SEL,
rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK,
rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK,
rockchip_combphy_updatel(priv, RK3568_PHYREG13_RESISTER_MASK, val,
rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32);
rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32);
rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, val, RK3568_PHYREG33);
rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK,
rockchip_combphy_updatel(priv, RK3568_PHYREG15_SSC_CNT_MASK,
rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK,
rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK,
rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val,
rockchip_combphy_updatel(priv, RK3568_PHYREG13_RESISTER_MASK, val,
rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32);
rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32);
rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, BIT(3),