rnandc
struct rnandc *rnandc = to_rnandc(chip->controller);
dev_err(rnandc->dev, "Unsupported page size\n");
dev_err(rnandc->dev, "Unsupported ECC chunk size\n");
dev_err(rnandc->dev, "Unsupported ECC strength\n");
struct rnandc *rnandc = to_rnandc(chip->controller);
dev_err(rnandc->dev, "No minimum ECC strength\n");
struct rnandc *rnandc = to_rnandc(chip->controller);
dev_err(rnandc->dev, "Small page devices not supported\n");
dev_err(rnandc->dev, "Unsupported memory organization\n");
dev_err(rnandc->dev, "ECC initialization failed (%d)\n", ret);
static int rnandc_alloc_dma_buf(struct rnandc *rnandc,
list_for_each_entry_safe(entry, temp, &rnandc->chips, node) {
if (rnandc->buf && rnandc->buf_sz < max_len) {
devm_kfree(rnandc->dev, rnandc->buf);
rnandc->buf = NULL;
if (!rnandc->buf) {
rnandc->buf_sz = max_len;
rnandc->buf = devm_kmalloc(rnandc->dev, max_len,
if (!rnandc->buf)
static int rnandc_chip_init(struct rnandc *rnandc, struct device_node *np)
dev_err(rnandc->dev, "Invalid reg property (%d)\n", ret);
rnand = devm_kzalloc(rnandc->dev, struct_size(rnand, sels, nsels),
dev_err(rnandc->dev, "Incomplete reg property (%d)\n", ret);
dev_err(rnandc->dev, "Invalid reg property (%d)\n", cs);
if (test_and_set_bit(cs, &rnandc->assigned_cs)) {
dev_err(rnandc->dev, "CS %d already assigned\n", cs);
chip->controller = &rnandc->controller;
mtd->dev.parent = rnandc->dev;
dev_err(rnandc->dev, "Missing MTD label\n");
dev_err(rnandc->dev, "Failed to scan the NAND chip (%d)\n", ret);
ret = rnandc_alloc_dma_buf(rnandc, mtd);
dev_err(rnandc->dev, "Failed to register MTD device (%d)\n", ret);
list_add_tail(&rnand->node, &rnandc->chips);
static void rnandc_chips_cleanup(struct rnandc *rnandc)
list_for_each_entry_safe(entry, temp, &rnandc->chips, node) {
static int rnandc_chips_init(struct rnandc *rnandc)
for_each_child_of_node_scoped(rnandc->dev->of_node, np) {
ret = rnandc_chip_init(rnandc, np);
rnandc_chips_cleanup(rnandc);
struct rnandc *rnandc;
rnandc = devm_kzalloc(&pdev->dev, sizeof(*rnandc), GFP_KERNEL);
if (!rnandc)
rnandc->dev = &pdev->dev;
nand_controller_init(&rnandc->controller);
rnandc->controller.ops = &rnandc_ops;
INIT_LIST_HEAD(&rnandc->chips);
init_completion(&rnandc->complete);
rnandc->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(rnandc->regs))
return PTR_ERR(rnandc->regs);
rnandc->ext_clk_rate = clk_get_rate(eclk);
rnandc_dis_interrupts(rnandc);
rnandc->use_polling = true;
"renesas-nand-controller", rnandc);
rnandc_clear_fifo(rnandc);
platform_set_drvdata(pdev, rnandc);
ret = rnandc_chips_init(rnandc);
struct rnandc *rnandc = platform_get_drvdata(pdev);
rnandc_chips_cleanup(rnandc);
static inline struct rnandc *to_rnandc(struct nand_controller *ctrl)
return container_of(ctrl, struct rnandc, controller);
static void rnandc_dis_correction(struct rnandc *rnandc)
control = readl_relaxed(rnandc->regs + CONTROL_REG);
writel_relaxed(control, rnandc->regs + CONTROL_REG);
static void rnandc_en_correction(struct rnandc *rnandc)
control = readl_relaxed(rnandc->regs + CONTROL_REG);
writel_relaxed(control, rnandc->regs + CONTROL_REG);
static void rnandc_clear_status(struct rnandc *rnandc)
writel_relaxed(0, rnandc->regs + INT_STATUS_REG);
writel_relaxed(0, rnandc->regs + ECC_STAT_REG);
writel_relaxed(0, rnandc->regs + ECC_CNT_REG);
static void rnandc_dis_interrupts(struct rnandc *rnandc)
writel_relaxed(0, rnandc->regs + INT_MASK_REG);
static void rnandc_en_interrupts(struct rnandc *rnandc, u32 val)
if (!rnandc->use_polling)
writel_relaxed(val, rnandc->regs + INT_MASK_REG);
static void rnandc_clear_fifo(struct rnandc *rnandc)
writel_relaxed(FIFO_INIT, rnandc->regs + FIFO_INIT_REG);
struct rnandc *rnandc = to_rnandc(chip->controller);
if (chip == rnandc->selected_chip && die_nr == rnand->selected_die)
rnandc_clear_status(rnandc);
writel_relaxed(MEM_CTRL_CS(cs) | MEM_CTRL_DIS_WP(cs), rnandc->regs + MEM_CTRL_REG);
writel_relaxed(rnand->control, rnandc->regs + CONTROL_REG);
writel_relaxed(rnand->ecc_ctrl, rnandc->regs + ECC_CTRL_REG);
writel_relaxed(rnand->timings_asyn, rnandc->regs + TIMINGS_ASYN_REG);
writel_relaxed(rnand->tim_seq0, rnandc->regs + TIM_SEQ0_REG);
writel_relaxed(rnand->tim_seq1, rnandc->regs + TIM_SEQ1_REG);
writel_relaxed(rnand->tim_gen_seq0, rnandc->regs + TIM_GEN_SEQ0_REG);
writel_relaxed(rnand->tim_gen_seq1, rnandc->regs + TIM_GEN_SEQ1_REG);
writel_relaxed(rnand->tim_gen_seq2, rnandc->regs + TIM_GEN_SEQ2_REG);
writel_relaxed(rnand->tim_gen_seq3, rnandc->regs + TIM_GEN_SEQ3_REG);
rnandc->selected_chip = chip;
static void rnandc_trigger_op(struct rnandc *rnandc, struct rnandc_op *rop)
writel_relaxed(rop->addr0_col, rnandc->regs + ADDR0_COL_REG);
writel_relaxed(rop->addr0_row, rnandc->regs + ADDR0_ROW_REG);
writel_relaxed(rop->addr1_col, rnandc->regs + ADDR1_COL_REG);
writel_relaxed(rop->addr1_row, rnandc->regs + ADDR1_ROW_REG);
writel_relaxed(rop->ecc_offset, rnandc->regs + ECC_OFFSET_REG);
writel_relaxed(rop->gen_seq_ctrl, rnandc->regs + GEN_SEQ_CTRL_REG);
writel_relaxed(DATA_SIZE(rop->len), rnandc->regs + DATA_SIZE_REG);
writel_relaxed(rop->command, rnandc->regs + COMMAND_REG);
static void rnandc_trigger_dma(struct rnandc *rnandc)
DMA_CTRL_START, rnandc->regs + DMA_CTRL_REG);
struct rnandc *rnandc = private;
rnandc_dis_interrupts(rnandc);
complete(&rnandc->complete);
static int rnandc_wait_end_of_op(struct rnandc *rnandc,
ret = readl_poll_timeout(rnandc->regs + STATUS_REG, status,
dev_err(rnandc->dev, "Operation timed out, status: 0x%08x\n",
static int rnandc_wait_end_of_io(struct rnandc *rnandc,
if (rnandc->use_polling) {
ret = readl_poll_timeout(rnandc->regs + INT_STATUS_REG, status,
ret = wait_for_completion_timeout(&rnandc->complete,
struct rnandc *rnandc = to_rnandc(chip->controller);
rnandc_clear_status(rnandc);
reinit_completion(&rnandc->complete);
rnandc_en_interrupts(rnandc, INT_DMA_ENDED);
rnandc_en_correction(rnandc);
dma_addr = dma_map_single(rnandc->dev, rnandc->buf, mtd->writesize,
if (dma_mapping_error(rnandc->dev, dma_addr))
writel(dma_addr, rnandc->regs + DMA_ADDR_LOW_REG);
writel(mtd->writesize, rnandc->regs + DMA_CNT_REG);
writel(DMA_TLVL_MAX, rnandc->regs + DMA_TLVL_REG);
rnandc_trigger_op(rnandc, &rop);
rnandc_trigger_dma(rnandc);
ret = rnandc_wait_end_of_io(rnandc, chip);
dma_unmap_single(rnandc->dev, dma_addr, mtd->writesize, DMA_FROM_DEVICE);
rnandc_dis_correction(rnandc);
dev_err(rnandc->dev, "Read page operation never ending\n");
ecc_stat = readl_relaxed(rnandc->regs + ECC_STAT_REG);
bf = nand_check_erased_ecc_chunk(rnandc->buf + off,
bf = ECC_CNT(cs, readl_relaxed(rnandc->regs + ECC_CNT_REG));
memcpy(buf, rnandc->buf, mtd->writesize);
struct rnandc *rnandc = to_rnandc(chip->controller);
rnandc_clear_status(rnandc);
rnandc_en_correction(rnandc);
rnandc_trigger_op(rnandc, &rop);
while (!FIFO_STATE_C_EMPTY(readl(rnandc->regs + FIFO_STATE_REG)))
while (FIFO_STATE_R_EMPTY(readl(rnandc->regs + FIFO_STATE_REG)))
ioread32_rep(rnandc->regs + FIFO_DATA_REG, bufpoi + page_off,
if (!FIFO_STATE_R_EMPTY(readl(rnandc->regs + FIFO_STATE_REG))) {
dev_err(rnandc->dev, "Clearing residual data in the read FIFO\n");
rnandc_clear_fifo(rnandc);
ret = rnandc_wait_end_of_op(rnandc, chip);
rnandc_dis_correction(rnandc);
dev_err(rnandc->dev, "Read subpage operation never ending\n");
ecc_stat = readl_relaxed(rnandc->regs + ECC_STAT_REG);
bf = ECC_CNT(cs, readl_relaxed(rnandc->regs + ECC_CNT_REG));
struct rnandc *rnandc = to_rnandc(chip->controller);
memcpy(rnandc->buf, buf, mtd->writesize);
rnandc_clear_status(rnandc);
reinit_completion(&rnandc->complete);
rnandc_en_interrupts(rnandc, INT_MEM_RDY(cs));
rnandc_en_correction(rnandc);
dma_addr = dma_map_single(rnandc->dev, (void *)rnandc->buf, mtd->writesize,
if (dma_mapping_error(rnandc->dev, dma_addr))
writel(dma_addr, rnandc->regs + DMA_ADDR_LOW_REG);
writel(mtd->writesize, rnandc->regs + DMA_CNT_REG);
writel(DMA_TLVL_MAX, rnandc->regs + DMA_TLVL_REG);
rnandc_trigger_op(rnandc, &rop);
rnandc_trigger_dma(rnandc);
ret = rnandc_wait_end_of_io(rnandc, chip);
dma_unmap_single(rnandc->dev, dma_addr, mtd->writesize, DMA_TO_DEVICE);
rnandc_dis_correction(rnandc);
dev_err(rnandc->dev, "Write page operation never ending\n");
struct rnandc *rnandc = to_rnandc(chip->controller);
rnandc_clear_status(rnandc);
rnandc_en_correction(rnandc);
rnandc_trigger_op(rnandc, &rop);
while (FIFO_STATE_W_FULL(readl(rnandc->regs + FIFO_STATE_REG)))
iowrite32_rep(rnandc->regs + FIFO_DATA_REG, bufpoi + page_off,
while (!FIFO_STATE_W_EMPTY(readl(rnandc->regs + FIFO_STATE_REG)))
ret = rnandc_wait_end_of_op(rnandc, chip);
rnandc_dis_correction(rnandc);
dev_err(rnandc->dev, "Write subpage operation never ending\n");
struct rnandc *rnandc = to_rnandc(chip->controller);
dev_err(rnandc->dev, "Cannot handle more than one wait delay\n");
rnandc_trigger_op(rnandc, &rop);
while (!FIFO_STATE_C_EMPTY(readl(rnandc->regs + FIFO_STATE_REG)))
while (FIFO_STATE_R_EMPTY(readl(rnandc->regs + FIFO_STATE_REG)))
ioread32_rep(rnandc->regs + FIFO_DATA_REG, rop.buf, words);
last_bytes = readl_relaxed(rnandc->regs + FIFO_DATA_REG);
if (!FIFO_STATE_R_EMPTY(readl(rnandc->regs + FIFO_STATE_REG))) {
dev_warn(rnandc->dev,
rnandc_clear_fifo(rnandc);
while (FIFO_STATE_W_FULL(readl(rnandc->regs + FIFO_STATE_REG)))
iowrite32_rep(rnandc->regs + FIFO_DATA_REG, rop.buf,
writel_relaxed(last_bytes, rnandc->regs + FIFO_DATA_REG);
while (!FIFO_STATE_W_EMPTY(readl(rnandc->regs + FIFO_STATE_REG)))
ret = rnandc_wait_end_of_op(rnandc, chip);
struct rnandc *rnandc = to_rnandc(chip->controller);
unsigned int period_ns = 1000000000 / rnandc->ext_clk_rate;
dev_err(rnandc->dev, "Read and write hold times must be identical\n");