rdmsrq_safe_on_cpu
ret = rdmsrq_safe_on_cpu(cpu, MSR_IA32_RTIT_CTL, &ctl);
if (rdmsrq_safe_on_cpu(cpu, domain->discovery_base, &base))
int rdmsrq_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q);
ret = rdmsrq_safe_on_cpu(cpu, MSR_AMD_CPPC_CAP1, &val);
err = rdmsrq_safe_on_cpu(cpunum, reg->address, val);
err = rdmsrq_safe_on_cpu(cpunum, reg->address, &rd_val);
err = rdmsrq_safe_on_cpu(cpu, reg, &data);
EXPORT_SYMBOL(rdmsrq_safe_on_cpu);
ret = rdmsrq_safe_on_cpu(cpu, MSR_AMD_CPPC_CAP1, &cap1);
int ret = rdmsrq_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1,
err = rdmsrq_safe_on_cpu(cpu, MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
err = rdmsrq_safe_on_cpu(cpu, tdp_msr, &tdp_ratio);
err = rdmsrq_safe_on_cpu(cpu, MSR_TURBO_ACTIVATION_RATIO, &tar);
err = rdmsrq_safe_on_cpu(id, 0x17, &val);
err = rdmsrq_safe_on_cpu(id, 0xee, &val);
err = rdmsrq_safe_on_cpu(tdata->cpu, MSR_IA32_TEMPERATURE_TARGET, &msrval);
ret = rdmsrq_safe_on_cpu(tdata->cpu, MSR_IA32_TEMPERATURE_TARGET, &val);
err = rdmsrq_safe_on_cpu(cpu, tdata->status_reg, &val);
err = rdmsrq_safe_on_cpu(data->id, data->msr_temp, &val);
err = rdmsrq_safe_on_cpu(data->id, data->msr_temp, &val);
err = rdmsrq_safe_on_cpu(data->id, data->msr_vid, &val);
ret = rdmsrq_safe_on_cpu(msr_cmd->logical_cpu,
if (rdmsrq_safe_on_cpu(cpu, ra->reg.msr, &ra->value)) {
err = rdmsrq_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &msrval.q);
err = rdmsrq_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &val.q);
err = rdmsrq_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &val.q);
err = rdmsrq_safe_on_cpu(cpu, msr, &val.q);