rdlp
if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
val = rdlp(mp, off);
u32 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
rdlp(mp, RX_DISCARD_FRAME_CNT);
rdlp(mp, RX_OVERRUN_FRAME_CNT);
p->rx_discard += rdlp(mp, RX_DISCARD_FRAME_CNT);
p->rx_overrun += rdlp(mp, RX_OVERRUN_FRAME_CNT);
u32 val = rdlp(mp, SDMA_CONFIG);
val = rdlp(mp, SDMA_CONFIG);
temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4;
port_status = rdlp(mp, PORT_STATUS);
unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE;
int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask;
int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
~(rdlp(mp, TXQ_COMMAND) & 0xff);
port_status = rdlp(mp, PORT_STATUS);
pscr = rdlp(mp, PORT_SERIAL_CONTROL);
rdlp(mp, INT_CAUSE_EXT);
u32 ps = rdlp(mp, PORT_STATUS);
data = rdlp(mp, PORT_SERIAL_CONTROL);
rdlp(mp, INT_MASK);
rdlp(mp, INT_MASK);
pscr = rdlp(mp, PORT_SERIAL_CONTROL);
psc1r = rdlp(mp, PORT_SERIAL_CONTROL1);
rdlp(mp, INT_MASK);
while (rdlp(mp, RXQ_COMMAND) & mask)
while (rdlp(mp, TXQ_COMMAND) & mask)