rd_reg32
return FIELD_GET(CSTA_MOO, rd_reg32(&ctrlpriv->jr[0]->perfmon.status));
cha_vid = rd_reg32(&perfmon->cha_id_ls);
cha_inst = rd_reg32(&perfmon->cha_num_ls);
aes_rn = rd_reg32(&perfmon->cha_rev_ls) & CHA_ID_LS_AES_MASK;
aesa = rd_reg32(&vreg->aesa);
mdha = rd_reg32(&vreg->mdha);
des_inst = rd_reg32(&vreg->desa) & CHA_VER_NUM_MASK;
ccha_inst = rd_reg32(&vreg->ccha) & CHA_VER_NUM_MASK;
ptha_inst = rd_reg32(&vreg->ptha) & CHA_VER_NUM_MASK;
cha_vid = rd_reg32(&priv->ctrl->perfmon.cha_id_ls);
cha_inst = rd_reg32(&priv->ctrl->perfmon.cha_num_ls);
aesa = rd_reg32(&priv->ctrl->vreg.aesa);
mdha = rd_reg32(&priv->ctrl->vreg.mdha);
des_inst = rd_reg32(&priv->ctrl->vreg.desa) & CHA_VER_NUM_MASK;
md_vid = (rd_reg32(&perfmon->cha_id_ls) &
md_inst = (rd_reg32(&perfmon->cha_num_ls) &
u32 mdha = rd_reg32(&priv->jr[0]->vreg.mdha);
pk_inst = (rd_reg32(&priv->jr[0]->perfmon.cha_num_ls) &
pkha = rd_reg32(&priv->jr[0]->vreg.pkha);
rng_inst = (rd_reg32(&priv->jr[0]->perfmon.cha_num_ls) &
rng_inst = rd_reg32(&priv->jr[0]->vreg.rng) & CHA_VER_NUM_MASK;
rng_inst = (rd_reg32(&priv->jr[0]->perfmon.cha_num_ls) &
rng_inst = rd_reg32(&priv->jr[0]->vreg.rng) & CHA_VER_NUM_MASK;
scfgr = rd_reg32(&ctrl->scfgr);
comp_params = rd_reg32(&perfmon->comp_parms_ls);
(rd_reg32(&perfmon->cha_num_ls) & CHA_ID_LS_AES_MASK);
(rd_reg32(&vreg->aesa) & CHA_VER_MISC_AES_NUM_MASK);
caam_id = (u64)rd_reg32(&perfmon->caam_id_ms) << 32 |
(u64)rd_reg32(&perfmon->caam_id_ls);
while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) &&
while (!(rd_reg32(&ctrl->deco_rq) & DECORR_DEN0) &&
deco_dbg_reg = rd_reg32(&deco->desc_dbg);
deco_state = (rd_reg32(&deco->dbg_exec) &
*status = rd_reg32(&deco->op_status_hi) &
rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_MASK;
rtsdctl = rd_reg32(&r4tst->rtsdctl);
ccbvid = rd_reg32(&perfmon->ccb_id);
id_ms = rd_reg32(&perfmon->caam_id_ms);
rng_vid = (rd_reg32(&perfmon->cha_id_ls) &
rng_vid = (rd_reg32(&vreg->rng) & CHA_VER_VID_MASK) >>
rd_reg32(&ctrl->r4tst[0].rdsta);
rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_MASK;
state->mcr = rd_reg32(&ctrl->mcr);
state->scfgr = rd_reg32(&ctrl->scfgr);
deco_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) &
rd_reg32(&ctrl->deco_mid[i].liodn_ms);
rd_reg32(&ctrl->deco_mid[i].liodn_ls);
jr_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) &
rd_reg32(&ctrl->jr_mid[i].liodn_ms);
rd_reg32(&ctrl->jr_mid[i].liodn_ls);
deco_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) &
jr_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) &
caam_little_end = !(bool)(rd_reg32(&perfmon->status) &
comp_params = rd_reg32(&perfmon->comp_parms_ms);
rd_reg32(&ctrl->mcr) & MCFGR_LONG_PTR)
if ((rd_reg32(&jrp->rregs->jrintstatus) & JRINT_ERR_HALT_MASK) !=
u32 halt_status = rd_reg32(&jrp->rregs->jrintstatus) &
while ((rd_reg32(&jrp->rregs->jrcommand) & JRCR_RESET) && --timeout)
irqstate = rd_reg32(&jrp->rregs->jrintstatus);
(outring_used = rd_reg32(&jrp->rregs->outring_used))) {
jrp->inpring_avail = rd_reg32(&jrp->rregs->inpring_avail);
if (rd_reg32(&jrp->rregs->jrintstatus) & JRINT_ERR_HALT_INPROGRESS)
while (((rd_reg32(&jrp->rregs->jrintstatus) & JRINT_ERR_HALT_MASK) ==