drivers/media/platform/qcom/iris/iris_vpu_common.c

18

#define CTRL_INIT (CPU_CS_BASE_OFFS + 0x48)

drivers/media/platform/qcom/iris/iris_vpu_common.c

19

#define CTRL_STATUS (CPU_CS_BASE_OFFS + 0x4C)

drivers/media/platform/qcom/iris/iris_vpu_common.c

25

#define QTBL_INFO (CPU_CS_BASE_OFFS + 0x50)

drivers/media/platform/qcom/iris/iris_vpu_common.c

28

#define QTBL_ADDR (CPU_CS_BASE_OFFS + 0x54)

drivers/media/platform/qcom/iris/iris_vpu_common.c

29

#define CPU_CS_SCIACMDARG3 (CPU_CS_BASE_OFFS + 0x58)

drivers/media/platform/qcom/iris/iris_vpu_common.c

30

#define SFR_ADDR (CPU_CS_BASE_OFFS + 0x5C)

drivers/media/platform/qcom/iris/iris_vpu_common.c

31

#define UC_REGION_ADDR (CPU_CS_BASE_OFFS + 0x64)

drivers/media/platform/qcom/iris/iris_vpu_common.c

32

#define UC_REGION_SIZE (CPU_CS_BASE_OFFS + 0x68)

drivers/media/platform/qcom/iris/iris_vpu_register_defines.h

26

#define CPU_CS_A2HSOFTINTCLR (CPU_CS_BASE_OFFS + 0x1C)

drivers/media/platform/qcom/iris/iris_vpu_register_defines.h

29

#define CPU_CS_H2XSOFTINTEN (CPU_CS_BASE_OFFS + 0x148)

drivers/media/platform/qcom/iris/iris_vpu_register_defines.h

35

#define CPU_CS_AHB_BRIDGE_SYNC_RESET (CPU_CS_BASE_OFFS + 0x160)

drivers/media/platform/qcom/iris/iris_vpu_register_defines.h

39

#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168)