rfcr
out_8(¶m->rfcr, 0x10);
u8 rfcr;
out_8(&i2c_ram->rfcr, I2C_EB);
out_8(&i2c_ram->rfcr, I2C_EB_CPM2);
u_char rfcr; /* Rx function code */
writeb(RCAR_CAN_RFCR_RFE, &priv->regs->rfcr);
u8 rfcr, isr;
rfcr = readb(&priv->regs->rfcr);
if (rfcr & RCAR_CAN_RFCR_RFEST)
u8 rfcr; /* Receive FIFO Control Register */
u32 rfcr;
rfcr = readl(ioaddr + RxFilterAddr) & RFCR_RESET_SAVE;
rfcr |= readl(ioaddr + RxFilterAddr) & ~RFCR_RESET_SAVE;
writel(rfcr, ioaddr + RxFilterAddr);
u32 rfcr;
rfcr = readl(ioaddr + RxFilterAddr);
writel(rfcr, ioaddr + RxFilterAddr);
u8 __iomem *rfcr = dev->base + RFCR;
val = (readl(rfcr) & and_mask) | or_mask;
writel(val & ~RFCR_RFEN, rfcr);
writel(val, rfcr);
p_common->rx_carrier_errors += port_stats.eth.rfcr;
u64 rfcr;
rfcrSave = sr32(rfcr);
sw32(rfcr, rfcrSave & ~RFEN);
sw32(rfcr, i << RFADDR_shift);
sw32(rfcr, rfcrSave | RFEN);
sw32(rfcr, (u32)(0x00000004 + i) << RFADDR_shift);
sw32(rfcr, RFEN | rx_mode);
sw32(rfcr, 0);
rfcrSave = sr32(rfcr);
sw32(rfcr, rfcrSave & ~RFEN);
sw32(rfcr, (i << RFADDR_shift));
sw32(rfcr, rfcrSave | RFEN);
iowrite8(CPMFCR_EB | CPMFCR_GBL, &mspi->pram->rfcr);
u8 rfcr; /* Rx function code */
u32 tfcr, rfcr;
regmap_read(esai_priv->regmap, REG_ESAI_RFCR, &rfcr);
enabled[rx] = rfcr & ESAI_xFCR_xFEN;