arch/arm64/include/asm/kvm_host.h

1637

struct resx get_reg_fixed_bits(struct kvm *kvm, enum vcpu_sysreg reg);

arch/arm64/include/asm/kvm_host.h

632

struct resx mask[NR_SYS_REGS - __SANITISED_REG_START__];

arch/arm64/include/asm/kvm_host.h

635

static inline struct resx __kvm_get_sysreg_resx(struct kvm_arch *arch,

arch/arm64/include/asm/kvm_host.h

645

return (struct resx){};

arch/arm64/include/asm/kvm_host.h

651

enum vcpu_sysreg sr, struct resx resx)

arch/arm64/include/asm/kvm_host.h

653

arch->sysreg_masks->mask[sr - __SANITISED_REG_START__] = resx;

arch/arm64/include/asm/kvm_host.h

656

#define kvm_set_sysreg_resx(k, sr, resx) \

arch/arm64/include/asm/kvm_host.h

657

__kvm_set_sysreg_resx(&(k)->arch, (sr), (resx))

arch/arm64/kvm/config.c

1281

int map_size, u64 resx, const char *str)

arch/arm64/kvm/config.c

1291

if (!((map[i].flags & FORCE_RESx) && (map[i].bits & resx)))

arch/arm64/kvm/config.c

1294

if (mask != ~resx)

arch/arm64/kvm/config.c

1296

str, mask ^ ~resx);

arch/arm64/kvm/config.c

1347

static struct resx compute_resx_bits(struct kvm *kvm,

arch/arm64/kvm/config.c

1354

struct resx resx = {};

arch/arm64/kvm/config.c

1381

resx.res1 |= bits;

arch/arm64/kvm/config.c

1383

resx.res0 |= bits;

arch/arm64/kvm/config.c

1387

return resx;

arch/arm64/kvm/config.c

1390

static struct resx compute_reg_resx_bits(struct kvm *kvm,

arch/arm64/kvm/config.c

1395

struct resx resx;

arch/arm64/kvm/config.c

1397

resx = compute_resx_bits(kvm, r->bit_feat_map, r->bit_feat_map_sz,

arch/arm64/kvm/config.c

1401

resx.res0 |= r->feat_map.masks->res0;

arch/arm64/kvm/config.c

1402

resx.res1 |= r->feat_map.masks->res1;

arch/arm64/kvm/config.c

1411

resx.res0 |= compute_resx_bits(kvm, &r->feat_map, 1, require, exclude).res0;

arch/arm64/kvm/config.c

1412

resx.res1 &= ~resx.res0;

arch/arm64/kvm/config.c

1414

return resx;

arch/arm64/kvm/config.c

1419

struct resx resx;

arch/arm64/kvm/config.c

1427

resx = compute_resx_bits(kvm, r->bit_feat_map, r->bit_feat_map_sz,

arch/arm64/kvm/config.c

1430

return resx.res0 | resx.res1;

arch/arm64/kvm/config.c

1470

struct resx get_reg_fixed_bits(struct kvm *kvm, enum vcpu_sysreg reg)

arch/arm64/kvm/config.c

1472

struct resx resx;

arch/arm64/kvm/config.c

1476

resx = compute_reg_resx_bits(kvm, &hfgrtr_desc, 0, 0);

arch/arm64/kvm/config.c

1479

resx = compute_reg_resx_bits(kvm, &hfgwtr_desc, 0, 0);

arch/arm64/kvm/config.c

1482

resx = compute_reg_resx_bits(kvm, &hfgitr_desc, 0, 0);

arch/arm64/kvm/config.c

1485

resx = compute_reg_resx_bits(kvm, &hdfgrtr_desc, 0, 0);

arch/arm64/kvm/config.c

1488

resx = compute_reg_resx_bits(kvm, &hdfgwtr_desc, 0, 0);

arch/arm64/kvm/config.c

1491

resx = compute_reg_resx_bits(kvm, &hafgrtr_desc, 0, 0);

arch/arm64/kvm/config.c

1494

resx = compute_reg_resx_bits(kvm, &hfgrtr2_desc, 0, 0);

arch/arm64/kvm/config.c

1497

resx = compute_reg_resx_bits(kvm, &hfgwtr2_desc, 0, 0);

arch/arm64/kvm/config.c

1500

resx = compute_reg_resx_bits(kvm, &hfgitr2_desc, 0, 0);

arch/arm64/kvm/config.c

1503

resx = compute_reg_resx_bits(kvm, &hdfgrtr2_desc, 0, 0);

arch/arm64/kvm/config.c

1506

resx = compute_reg_resx_bits(kvm, &hdfgwtr2_desc, 0, 0);

arch/arm64/kvm/config.c

1509

resx = compute_reg_resx_bits(kvm, &hcrx_desc, 0, 0);

arch/arm64/kvm/config.c

1510

resx.res1 |= __HCRX_EL2_RES1;

arch/arm64/kvm/config.c

1513

resx = compute_reg_resx_bits(kvm, &hcr_desc, 0, 0);

arch/arm64/kvm/config.c

1517

resx = compute_reg_resx_bits(kvm, &sctlr2_desc, 0, 0);

arch/arm64/kvm/config.c

1520

resx = compute_reg_resx_bits(kvm, &tcr2_el2_desc, 0, 0);

arch/arm64/kvm/config.c

1523

resx = compute_reg_resx_bits(kvm, &sctlr_el1_desc, 0, 0);

arch/arm64/kvm/config.c

1526

resx = compute_reg_resx_bits(kvm, &sctlr_el2_desc, 0, 0);

arch/arm64/kvm/config.c

1529

resx = compute_reg_resx_bits(kvm, &mdcr_el2_desc, 0, 0);

arch/arm64/kvm/config.c

1532

resx = compute_reg_resx_bits(kvm, &vtcr_el2_desc, 0, 0);

arch/arm64/kvm/config.c

1536

resx = (typeof(resx)){};

arch/arm64/kvm/config.c

1540

return resx;

arch/arm64/kvm/nested.c

1683

struct resx resx;

arch/arm64/kvm/nested.c

1685

resx = kvm_get_sysreg_resx(vcpu->kvm, sr);

arch/arm64/kvm/nested.c

1686

v &= ~resx.res0;

arch/arm64/kvm/nested.c

1687

v |= resx.res1;

arch/arm64/kvm/nested.c

1692

static __always_inline void set_sysreg_masks(struct kvm *kvm, int sr, struct resx resx)

arch/arm64/kvm/nested.c

1698

kvm_set_sysreg_resx(kvm, sr, resx);

arch/arm64/kvm/nested.c

1704

struct resx resx;

arch/arm64/kvm/nested.c

1717

resx = (typeof(resx)){};

arch/arm64/kvm/nested.c

1719

resx.res0 |= GENMASK(63, 56);

arch/arm64/kvm/nested.c

1721

resx.res0 |= VTTBR_CNP_BIT;

arch/arm64/kvm/nested.c

1722

set_sysreg_masks(kvm, VTTBR_EL2, resx);

arch/arm64/kvm/nested.c

1725

resx = get_reg_fixed_bits(kvm, VTCR_EL2);

arch/arm64/kvm/nested.c

1726

set_sysreg_masks(kvm, VTCR_EL2, resx);

arch/arm64/kvm/nested.c

1729

resx.res0 = GENMASK(63, 40) | GENMASK(30, 24);

arch/arm64/kvm/nested.c

1730

resx.res1 = BIT(31);

arch/arm64/kvm/nested.c

1731

set_sysreg_masks(kvm, VMPIDR_EL2, resx);

arch/arm64/kvm/nested.c

1734

resx = get_reg_fixed_bits(kvm, HCR_EL2);

arch/arm64/kvm/nested.c

1735

set_sysreg_masks(kvm, HCR_EL2, resx);

arch/arm64/kvm/nested.c

1738

resx = get_reg_fixed_bits(kvm, HCRX_EL2);

arch/arm64/kvm/nested.c

1739

set_sysreg_masks(kvm, HCRX_EL2, resx);

arch/arm64/kvm/nested.c

1742

resx = get_reg_fixed_bits(kvm, HFGRTR_EL2);

arch/arm64/kvm/nested.c

1743

set_sysreg_masks(kvm, HFGRTR_EL2, resx);

arch/arm64/kvm/nested.c

1744

resx = get_reg_fixed_bits(kvm, HFGWTR_EL2);

arch/arm64/kvm/nested.c

1745

set_sysreg_masks(kvm, HFGWTR_EL2, resx);

arch/arm64/kvm/nested.c

1748

resx = get_reg_fixed_bits(kvm, HDFGRTR_EL2);

arch/arm64/kvm/nested.c

1749

set_sysreg_masks(kvm, HDFGRTR_EL2, resx);

arch/arm64/kvm/nested.c

1750

resx = get_reg_fixed_bits(kvm, HDFGWTR_EL2);

arch/arm64/kvm/nested.c

1751

set_sysreg_masks(kvm, HDFGWTR_EL2, resx);

arch/arm64/kvm/nested.c

1754

resx = get_reg_fixed_bits(kvm, HFGITR_EL2);

arch/arm64/kvm/nested.c

1755

set_sysreg_masks(kvm, HFGITR_EL2, resx);

arch/arm64/kvm/nested.c

1758

resx = get_reg_fixed_bits(kvm, HAFGRTR_EL2);

arch/arm64/kvm/nested.c

1759

set_sysreg_masks(kvm, HAFGRTR_EL2, resx);

arch/arm64/kvm/nested.c

1762

resx = get_reg_fixed_bits(kvm, HFGRTR2_EL2);

arch/arm64/kvm/nested.c

1763

set_sysreg_masks(kvm, HFGRTR2_EL2, resx);

arch/arm64/kvm/nested.c

1764

resx = get_reg_fixed_bits(kvm, HFGWTR2_EL2);

arch/arm64/kvm/nested.c

1765

set_sysreg_masks(kvm, HFGWTR2_EL2, resx);

arch/arm64/kvm/nested.c

1768

resx = get_reg_fixed_bits(kvm, HDFGRTR2_EL2);

arch/arm64/kvm/nested.c

1769

set_sysreg_masks(kvm, HDFGRTR2_EL2, resx);

arch/arm64/kvm/nested.c

1770

resx = get_reg_fixed_bits(kvm, HDFGWTR2_EL2);

arch/arm64/kvm/nested.c

1771

set_sysreg_masks(kvm, HDFGWTR2_EL2, resx);

arch/arm64/kvm/nested.c

1774

resx = get_reg_fixed_bits(kvm, HFGITR2_EL2);

arch/arm64/kvm/nested.c

1775

set_sysreg_masks(kvm, HFGITR2_EL2, resx);

arch/arm64/kvm/nested.c

1778

resx = get_reg_fixed_bits(kvm, TCR2_EL2);

arch/arm64/kvm/nested.c

1779

set_sysreg_masks(kvm, TCR2_EL2, resx);

arch/arm64/kvm/nested.c

1782

resx = get_reg_fixed_bits(kvm, SCTLR_EL1);

arch/arm64/kvm/nested.c

1783

set_sysreg_masks(kvm, SCTLR_EL1, resx);

arch/arm64/kvm/nested.c

1786

resx = get_reg_fixed_bits(kvm, SCTLR_EL2);

arch/arm64/kvm/nested.c

1787

set_sysreg_masks(kvm, SCTLR_EL2, resx);

arch/arm64/kvm/nested.c

1790

resx = get_reg_fixed_bits(kvm, SCTLR2_EL1);

arch/arm64/kvm/nested.c

1791

set_sysreg_masks(kvm, SCTLR2_EL1, resx);

arch/arm64/kvm/nested.c

1792

resx = get_reg_fixed_bits(kvm, SCTLR2_EL2);

arch/arm64/kvm/nested.c

1793

set_sysreg_masks(kvm, SCTLR2_EL2, resx);

arch/arm64/kvm/nested.c

1796

resx = get_reg_fixed_bits(kvm, MDCR_EL2);

arch/arm64/kvm/nested.c

1797

set_sysreg_masks(kvm, MDCR_EL2, resx);

arch/arm64/kvm/nested.c

1800

resx.res0 = GENMASK(63, 20);

arch/arm64/kvm/nested.c

1801

resx.res1 = 0;

arch/arm64/kvm/nested.c

1803

resx.res0 |= CNTHCTL_CNTPMASK | CNTHCTL_CNTVMASK;

arch/arm64/kvm/nested.c

1805

resx.res0 |= CNTHCTL_ECV;

arch/arm64/kvm/nested.c

1807

resx.res0 |= (CNTHCTL_EL1TVT | CNTHCTL_EL1TVCT |

arch/arm64/kvm/nested.c

1811

resx.res0 |= GENMASK(11, 8);

arch/arm64/kvm/nested.c

1812

set_sysreg_masks(kvm, CNTHCTL_EL2, resx);

arch/arm64/kvm/nested.c

1815

resx.res0 = ICH_HCR_EL2_RES0;

arch/arm64/kvm/nested.c

1816

resx.res1 = ICH_HCR_EL2_RES1;

arch/arm64/kvm/nested.c

1818

resx.res0 |= ICH_HCR_EL2_TDIR;

arch/arm64/kvm/nested.c

1820

resx.res0 |= ICH_HCR_EL2_DVIM | ICH_HCR_EL2_vSGIEOICount;

arch/arm64/kvm/nested.c

1821

set_sysreg_masks(kvm, ICH_HCR_EL2, resx);

arch/arm64/kvm/nested.c

1824

resx.res0 = VNCR_EL2_RES0;

arch/arm64/kvm/nested.c

1825

resx.res1 = VNCR_EL2_RES1;

arch/arm64/kvm/nested.c

1826

set_sysreg_masks(kvm, VNCR_EL2, resx);

arch/arm64/kvm/sys_regs.c

5106

struct resx resx;

arch/arm64/kvm/sys_regs.c

5111

resx = kvm_get_sysreg_resx(kvm, desc->reg);

arch/arm64/kvm/sys_regs.c

5114

desc->name, resx.res0, resx.res1);

drivers/input/touchscreen/ili210x.c

380

u16 resx, resy;

drivers/input/touchscreen/ili210x.c

387

resx = le16_to_cpup((__le16 *)rs);

drivers/input/touchscreen/ili210x.c

391

if (!resx || resx == 0xffff || !resy || resy == 0xffff)

drivers/input/touchscreen/ili210x.c

403

resx = 16384;

drivers/input/touchscreen/ili210x.c

407

input_abs_set_max(priv->input, ABS_X, resx - 1);

drivers/input/touchscreen/ili210x.c

409

input_abs_set_max(priv->input, ABS_MT_POSITION_X, resx - 1);