arch/arm64/kvm/sys_regs.c

2579

EL2_REG_FILTERED(name, bad_vncr_trap, reset_val, 0, vis)

arch/arm64/kvm/sys_regs.c

2585

SYS_REG_USER_FILTER(name, access_arch_timer, reset_val, 0, \

arch/arm64/kvm/sys_regs.c

3108

{ SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 },

arch/arm64/kvm/sys_regs.c

3109

{ SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 },

arch/arm64/kvm/sys_regs.c

3127

{ SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1,

arch/arm64/kvm/sys_regs.c

3140

{ SYS_DESC(SYS_DBGVCR32_EL2), undef_access, reset_val, DBGVCR32_EL2, 0 },

arch/arm64/kvm/sys_regs.c

3285

{ SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },

arch/arm64/kvm/sys_regs.c

3287

{ SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 },

arch/arm64/kvm/sys_regs.c

3288

{ SYS_DESC(SYS_SCTLR2_EL1), access_vm_reg, reset_val, SCTLR2_EL1, 0,

arch/arm64/kvm/sys_regs.c

3294

{ SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility },

arch/arm64/kvm/sys_regs.c

3300

{ SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 },

arch/arm64/kvm/sys_regs.c

3301

{ SYS_DESC(SYS_TCR2_EL1), access_vm_reg, reset_val, TCR2_EL1, 0,

arch/arm64/kvm/sys_regs.c

3379

{ SYS_DESC(SYS_VBAR_EL1), access_rw, reset_val, VBAR_EL1, 0 },

arch/arm64/kvm/sys_regs.c

3380

{ SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 },

arch/arm64/kvm/sys_regs.c

3408

{ SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },

arch/arm64/kvm/sys_regs.c

3415

{ SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0},

arch/arm64/kvm/sys_regs.c

3428

{ SYS_DESC(SYS_SVCR), undef_access, reset_val, SVCR, 0, .visibility = sme_visibility },

arch/arm64/kvm/sys_regs.c

3429

{ SYS_DESC(SYS_FPMR), undef_access, reset_val, FPMR, 0, .visibility = fp8_visibility },

arch/arm64/kvm/sys_regs.c

3468

.reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 },

arch/arm64/kvm/sys_regs.c

3637

.reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 },

arch/arm64/kvm/sys_regs.c

3641

EL2_REG(SCTLR_EL2, access_rw, reset_val, SCTLR_EL2_RES1),

arch/arm64/kvm/sys_regs.c

3642

EL2_REG(ACTLR_EL2, access_rw, reset_val, 0),

arch/arm64/kvm/sys_regs.c

3643

EL2_REG_FILTERED(SCTLR2_EL2, access_vm_reg, reset_val, 0,

arch/arm64/kvm/sys_regs.c

3647

EL2_REG(CPTR_EL2, access_rw, reset_val, CPTR_NVHE_EL2_RES1),

arch/arm64/kvm/sys_regs.c

3648

EL2_REG_VNCR(HSTR_EL2, reset_val, 0),

arch/arm64/kvm/sys_regs.c

3651

EL2_REG_VNCR(HFGITR_EL2, reset_val, 0),

arch/arm64/kvm/sys_regs.c

3652

EL2_REG_VNCR(HACR_EL2, reset_val, 0),

arch/arm64/kvm/sys_regs.c

3654

EL2_REG_FILTERED(ZCR_EL2, access_zcr_el2, reset_val, 0,

arch/arm64/kvm/sys_regs.c

3657

EL2_REG_VNCR(HCRX_EL2, reset_val, 0),

arch/arm64/kvm/sys_regs.c

3659

EL2_REG(TTBR0_EL2, access_rw, reset_val, 0),

arch/arm64/kvm/sys_regs.c

3660

EL2_REG(TTBR1_EL2, access_rw, reset_val, 0),

arch/arm64/kvm/sys_regs.c

3661

EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1),

arch/arm64/kvm/sys_regs.c

3662

EL2_REG_FILTERED(TCR2_EL2, access_rw, reset_val, TCR2_EL2_RES1,

arch/arm64/kvm/sys_regs.c

3664

EL2_REG_VNCR(VTTBR_EL2, reset_val, 0),

arch/arm64/kvm/sys_regs.c

3665

EL2_REG_VNCR(VTCR_EL2, reset_val, 0),

arch/arm64/kvm/sys_regs.c

3666

EL2_REG_FILTERED(VNCR_EL2, bad_vncr_trap, reset_val, 0,

arch/arm64/kvm/sys_regs.c

3678

EL2_REG_REDIR(SPSR_EL2, reset_val, 0),

arch/arm64/kvm/sys_regs.c

3679

EL2_REG_REDIR(ELR_EL2, reset_val, 0),

arch/arm64/kvm/sys_regs.c

3689

EL2_REG(AFSR0_EL2, access_rw, reset_val, 0),

arch/arm64/kvm/sys_regs.c

3690

EL2_REG(AFSR1_EL2, access_rw, reset_val, 0),

arch/arm64/kvm/sys_regs.c

3691

EL2_REG_REDIR(ESR_EL2, reset_val, 0),

arch/arm64/kvm/sys_regs.c

3693

{ SYS_DESC(SYS_FPEXC32_EL2), undef_access, reset_val, FPEXC32_EL2, 0x700 },

arch/arm64/kvm/sys_regs.c

3695

EL2_REG_REDIR(FAR_EL2, reset_val, 0),

arch/arm64/kvm/sys_regs.c

3696

EL2_REG(HPFAR_EL2, access_rw, reset_val, 0),

arch/arm64/kvm/sys_regs.c

3698

EL2_REG(MAIR_EL2, access_rw, reset_val, 0),

arch/arm64/kvm/sys_regs.c

3699

EL2_REG_FILTERED(PIRE0_EL2, access_rw, reset_val, 0,

arch/arm64/kvm/sys_regs.c

3701

EL2_REG_FILTERED(PIR_EL2, access_rw, reset_val, 0,

arch/arm64/kvm/sys_regs.c

3703

EL2_REG_FILTERED(POR_EL2, access_rw, reset_val, 0,

arch/arm64/kvm/sys_regs.c

3705

EL2_REG(AMAIR_EL2, access_rw, reset_val, 0),

arch/arm64/kvm/sys_regs.c

3718

EL2_REG(VBAR_EL2, access_rw, reset_val, 0),

arch/arm64/kvm/sys_regs.c

3758

EL2_REG(CONTEXTIDR_EL2, access_rw, reset_val, 0),

arch/arm64/kvm/sys_regs.c

3759

EL2_REG(TPIDR_EL2, access_rw, reset_val, 0),

arch/arm64/kvm/sys_regs.c

3761

EL2_REG_VNCR(CNTVOFF_EL2, reset_val, 0),

arch/arm64/kvm/sys_regs.c

3762

EL2_REG(CNTHCTL_EL2, access_rw, reset_val, 0),

drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

55

uint32_t reset_val = reset ? 1 : 0;

drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

58

REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, reset_val);

drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

62

REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, reset_val, 10, 5000);

drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

89

uint32_t reset_val;

drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

91

REG_GET(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, &reset_val);

drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

92

return (reset_val != 0);

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

397

uint32_t reset_val = reset ? 1 : 0;

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

400

REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, reset_val);

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

404

REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, reset_val, 10, 5000);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

382

uint32_t reset_val = reset ? 1 : 0;

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

385

REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, reset_val);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

389

REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, reset_val, 10, 5000);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

397

uint32_t reset_val;

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

399

REG_GET(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, &reset_val);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

400

return reset_val != 0;

drivers/gpu/drm/bridge/samsung-dsim.c

724

u32 reset_val = dsi->driver_data->reg_values[RESET_TYPE];

drivers/gpu/drm/bridge/samsung-dsim.c

727

samsung_dsim_write(dsi, DSIM_SWRST_REG, reset_val);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

260

u32 mask, reset_val, val;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

266

reset_val = 0xbabeface;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

269

reset_val = 0x100;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

288

(val & mask) == reset_val, 100, 10000);

drivers/infiniband/hw/efa/efa_com.c

1054

u32 reset_val = 0;

drivers/infiniband/hw/efa/efa_com.c

1073

EFA_SET(&reset_val, EFA_REGS_DEV_CTL_DEV_RESET, 1);

drivers/infiniband/hw/efa/efa_com.c

1074

EFA_SET(&reset_val, EFA_REGS_DEV_CTL_RESET_REASON, reset_reason);

drivers/infiniband/hw/efa/efa_com.c

1075

writel(reset_val, edev->reg_bar + EFA_REGS_DEV_CTL_OFF);

drivers/memory/stm32-fmc2-ebi.c

1003

.reset_val = FMC2_BXTR_ADDHLD_MAX,

drivers/memory/stm32-fmc2-ebi.c

1011

.reset_val = FMC2_BXTR_DATAST_MAX,

drivers/memory/stm32-fmc2-ebi.c

1019

.reset_val = FMC2_BXTR_BUSTURN_MAX + 1,

drivers/memory/stm32-fmc2-ebi.c

1032

.reset_val = FMC2_BTR_CLKDIV_MAX + 1,

drivers/memory/stm32-fmc2-ebi.c

1046

.reset_val = FMC2_BXTR_ADDSET_MAX,

drivers/memory/stm32-fmc2-ebi.c

1054

.reset_val = FMC2_BXTR_ADDHLD_MAX,

drivers/memory/stm32-fmc2-ebi.c

1062

.reset_val = FMC2_BXTR_DATAST_MAX,

drivers/memory/stm32-fmc2-ebi.c

1070

.reset_val = FMC2_BXTR_BUSTURN_MAX + 1,

drivers/memory/stm32-fmc2-ebi.c

1113

.reset_val = FMC2_BUSWIDTH_16,

drivers/memory/stm32-fmc2-ebi.c

1160

.reset_val = FMC2_BXTR_ADDSET_MAX,

drivers/memory/stm32-fmc2-ebi.c

1168

.reset_val = FMC2_BXTR_ADDHLD_MAX,

drivers/memory/stm32-fmc2-ebi.c

1176

.reset_val = FMC2_BXTR_DATAST_MAX,

drivers/memory/stm32-fmc2-ebi.c

1184

.reset_val = FMC2_BXTR_BUSTURN_MAX + 1,

drivers/memory/stm32-fmc2-ebi.c

1197

.reset_val = FMC2_CFGR_CLKDIV_MAX + 1,

drivers/memory/stm32-fmc2-ebi.c

1211

.reset_val = FMC2_BXTR_ADDSET_MAX,

drivers/memory/stm32-fmc2-ebi.c

1219

.reset_val = FMC2_BXTR_ADDHLD_MAX,

drivers/memory/stm32-fmc2-ebi.c

1227

.reset_val = FMC2_BXTR_DATAST_MAX,

drivers/memory/stm32-fmc2-ebi.c

1235

.reset_val = FMC2_BXTR_BUSTURN_MAX + 1,

drivers/memory/stm32-fmc2-ebi.c

1398

setup = prop->reset_val;

drivers/memory/stm32-fmc2-ebi.c

232

u32 reset_val;

drivers/memory/stm32-fmc2-ebi.c

948

.reset_val = FMC2_BUSWIDTH_16,

drivers/memory/stm32-fmc2-ebi.c

995

.reset_val = FMC2_BXTR_ADDSET_MAX,

drivers/net/ethernet/amazon/ena/ena_com.c

2353

u32 stat, timeout, cap, reset_val;

drivers/net/ethernet/amazon/ena/ena_com.c

2377

reset_val = ENA_REGS_DEV_CTL_DEV_RESET_MASK;

drivers/net/ethernet/amazon/ena/ena_com.c

2378

reset_val |= (reset_reason << ENA_REGS_DEV_CTL_RESET_REASON_SHIFT) &

drivers/net/ethernet/amazon/ena/ena_com.c

2380

writel(reset_val, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);

drivers/net/ethernet/amd/lance.c

476

int i, reset_val, lance_version;

drivers/net/ethernet/amd/lance.c

509

reset_val = inw(ioaddr+LANCE_RESET); /* Reset the LANCE */

drivers/net/ethernet/amd/lance.c

514

outw(reset_val, ioaddr+LANCE_RESET);

drivers/net/ethernet/amd/lance.c

605

short reset_val = inw(ioaddr+LANCE_RESET);

drivers/net/ethernet/amd/lance.c

606

dev->dma = dma_tbl[(reset_val >> 2) & 3];

drivers/net/ethernet/amd/lance.c

607

dev->irq = irq_tbl[(reset_val >> 4) & 7];

drivers/net/ethernet/qlogic/qed/qed_debug.c

1701

if (s_rbc_reset_defs[i].reset_val[dev_data->chip_id])

drivers/net/ethernet/qlogic/qed/qed_debug.c

1706

s_rbc_reset_defs[i].reset_val[chip_id]);

drivers/net/ethernet/qlogic/qed/qed_debug.c

286

u32 reset_val[MAX_CHIP_IDS];

drivers/net/ethernet/sun/niu.c

932

u64 reset_val, val_rd;

drivers/net/ethernet/sun/niu.c

939

reset_val = ENET_SERDES_RESET_0;

drivers/net/ethernet/sun/niu.c

945

reset_val = ENET_SERDES_RESET_1;

drivers/net/ethernet/sun/niu.c

979

nw64(ENET_SERDES_RESET, reset_val);

drivers/net/ethernet/sun/niu.c

982

val_rd &= ~reset_val;

drivers/power/supply/cw2015_battery.c

100

u8 reset_val;

drivers/power/supply/cw2015_battery.c

107

reset_val = reg_val;

drivers/power/supply/cw2015_battery.c

130

reset_val &= ~CW2015_MODE_RESTART;

drivers/power/supply/cw2015_battery.c

131

reg_val = reset_val | CW2015_MODE_RESTART;

drivers/power/supply/cw2015_battery.c

140

ret = regmap_write(cw_bat->regmap, CW2015_REG_MODE, reset_val);

drivers/power/supply/cw2015_battery.c

229

unsigned char reset_val;

drivers/power/supply/cw2015_battery.c

231

reset_val = CW2015_MODE_SLEEP;

drivers/power/supply/cw2015_battery.c

232

ret = regmap_write(cw_bat->regmap, CW2015_REG_MODE, reset_val);

drivers/power/supply/cw2015_battery.c

239

reset_val = CW2015_MODE_NORMAL;

drivers/power/supply/cw2015_battery.c

240

ret = regmap_write(cw_bat->regmap, CW2015_REG_MODE, reset_val);

drivers/power/supply/max17040_battery.c

103

.reset_val = 0x5400,

drivers/power/supply/max17040_battery.c

112

.reset_val = 0x5400,

drivers/power/supply/max17040_battery.c

121

.reset_val = 0x5400,

drivers/power/supply/max17040_battery.c

130

.reset_val = 0x5400,

drivers/power/supply/max17040_battery.c

160

return regmap_write(chip->regmap, MAX17040_CMD, chip->data.reset_val);

drivers/power/supply/max17040_battery.c

56

u16 reset_val;

drivers/power/supply/max17040_battery.c

67

.reset_val = 0x0054,

drivers/power/supply/max17040_battery.c

76

.reset_val = 0x0054,

drivers/power/supply/max17040_battery.c

85

.reset_val = 0x0054,

drivers/power/supply/max17040_battery.c

94

.reset_val = 0x0054,

drivers/scsi/hisi_sas/hisi_sas_v2_hw.c

1017

int i, reset_val;

drivers/scsi/hisi_sas/hisi_sas_v2_hw.c

1024

reset_val = 0x1fffff;

drivers/scsi/hisi_sas/hisi_sas_v2_hw.c

1026

reset_val = 0x7ffff;

drivers/scsi/hisi_sas/hisi_sas_v2_hw.c

1086

reset_val);

drivers/scsi/hisi_sas/hisi_sas_v2_hw.c

1088

reset_val);

drivers/scsi/hisi_sas/hisi_sas_v2_hw.c

1091

if (reset_val != (val & reset_val)) {

drivers/scsi/hisi_sas/hisi_sas_v2_hw.c

1098

reset_val);

drivers/scsi/hisi_sas/hisi_sas_v2_hw.c

1100

reset_val);

drivers/scsi/hisi_sas/hisi_sas_v2_hw.c

1104

if (val & reset_val) {

drivers/usb/cdns3/cdns3-gadget.c

715

u16 reset_val = EP_CMD_TDL_MAX + 1 - tdl;

drivers/usb/cdns3/cdns3-gadget.c

717

writel(EP_CMD_TDL_SET(reset_val) | EP_CMD_STDL,

include/linux/qed/qed_chain.h

498

u32 reset_val = p_chain->page_cnt - 1;

include/linux/qed/qed_chain.h

501

p_chain->pbl.c.u16.prod_page_idx = (u16)reset_val;

include/linux/qed/qed_chain.h

502

p_chain->pbl.c.u16.cons_page_idx = (u16)reset_val;

include/linux/qed/qed_chain.h

504

p_chain->pbl.c.u32.prod_page_idx = reset_val;

include/linux/qed/qed_chain.h

505

p_chain->pbl.c.u32.cons_page_idx = reset_val;

tools/testing/selftests/kvm/arm64/hypercalls.c

187

TEST_ASSERT(val == reg_info->reset_val,

tools/testing/selftests/kvm/arm64/hypercalls.c

189

reg_info->reg, reg_info->reset_val, val);

tools/testing/selftests/kvm/arm64/hypercalls.c

191

if (reg_info->reset_val)

tools/testing/selftests/kvm/arm64/hypercalls.c

34

uint64_t reset_val; /* Reset value for the register */

tools/testing/selftests/kvm/arm64/hypercalls.c

41

.reset_val = r##_RESET_VAL \

tools/testing/selftests/kvm/x86/msrs_test.c

121

__rdmsr(msr->index, msr->reset_val);

tools/testing/selftests/kvm/x86/msrs_test.c

125

__rdmsr(msr->index, msr->reset_val);

tools/testing/selftests/kvm/x86/msrs_test.c

16

const u64 reset_val;

tools/testing/selftests/kvm/x86/msrs_test.c

187

__wrmsr(msr->index, msr->reset_val);

tools/testing/selftests/kvm/x86/msrs_test.c

204

GUEST_SYNC(msr->reset_val);

tools/testing/selftests/kvm/x86/msrs_test.c

254

u64 reset_val = msrs[idx].reset_val;

tools/testing/selftests/kvm/x86/msrs_test.c

275

TEST_ASSERT(val == reset_val, "Wanted 0x%lx from get_reg(0x%x), got 0x%lx",

tools/testing/selftests/kvm/x86/msrs_test.c

276

reset_val, reg, val);

tools/testing/selftests/kvm/x86/msrs_test.c

29

.reset_val = reset, \

tools/testing/selftests/kvm/x86/msrs_test.c

290

u64 reset_val = msrs[idx].reset_val;

tools/testing/selftests/kvm/x86/msrs_test.c

302

vcpu_set_reg(vcpu, KVM_X86_REG_MSR(msr), reset_val);

tools/testing/selftests/kvm/x86/msrs_test.c

304

vcpu_set_msr(vcpu, msr, reset_val);

tools/testing/selftests/kvm/x86/msrs_test.c

307

TEST_ASSERT(val == reset_val, "Wanted 0x%lx from get_msr(0x%x), got 0x%lx",

tools/testing/selftests/kvm/x86/msrs_test.c

308

reset_val, msr, val);

tools/testing/selftests/kvm/x86/msrs_test.c

314

TEST_ASSERT(val == reset_val, "Wanted 0x%lx from get_reg(0x%x), got 0x%lx",

tools/testing/selftests/kvm/x86/msrs_test.c

315

reset_val, msr, val);