reset_prepare
.reset_prepare = hl_pci_reset_prepare,
.reset_prepare = ivpu_pm_reset_prepare_cb,
.reset_prepare = qaic_pci_reset_prepare,
.reset_prepare = virtblk_reset_prepare,
.reset_prepare = mhi_pci_reset_prepare,
if (cdx_drv && cdx_drv->reset_prepare)
cdx_drv->reset_prepare(cdx_dev);
.reset_prepare = hisi_qm_reset_prepare,
.reset_prepare = hisi_qm_reset_prepare,
.reset_prepare = hisi_qm_reset_prepare,
.reset_prepare = idxd_reset_prepare,
awake = reset_prepare(gt);
awake = reset_prepare(gt);
engine->reset.prepare = reset_prepare;
awake = reset_prepare(gt);
.reset_prepare = ipu6_pci_reset_prepare,
.reset_prepare = pdsc_reset_prepare,
.reset_prepare = eeh_reset_prepare,
.reset_prepare = hbg_pci_err_reset_prepare,
void (*reset_prepare)(struct hnae3_ae_dev *ae_dev,
if (ae_dev->ops && ae_dev->ops->reset_prepare)
ae_dev->ops->reset_prepare(ae_dev, HNAE3_FUNC_RESET);
if (ae_dev && ae_dev->ops && ae_dev->ops->reset_prepare)
ae_dev->ops->reset_prepare(ae_dev, HNAE3_FLR_RESET);
.reset_prepare = hns3_reset_prepare,
.reset_prepare = hclge_reset_prepare_general,
.reset_prepare = hclgevf_reset_prepare_general,
.reset_prepare = fm10k_io_reset_prepare,
.reset_prepare = i40e_pci_error_reset_prepare,
.reset_prepare = ice_pci_err_reset_prepare,
.reset_prepare = igbvf_io_prepare,
.reset_prepare = mlxsw_pci_reset_prepare,
.reset_prepare = ionic_reset_prepare,
.reset_prepare = mwifiex_pcie_reset_prepare,
.reset_prepare = nvme_reset_prepare,
if (err_handler && err_handler->reset_prepare)
err_handler->reset_prepare(dev);
.reset_prepare = hisi_sas_reset_prepare_v3_hw,
.reset_prepare = qla_pci_reset_prepare,
.reset_prepare = ipu7_pci_reset_prepare,
.reset_prepare = hisi_acc_vf_pci_reset_prepare,
if (!drv || !drv->reset_prepare)
ret = drv->reset_prepare(dev);
.reset_prepare = virtio_pci_reset_prepare,
void (*reset_prepare)(struct cdx_device *dev);
void (*reset_prepare)(struct pci_dev *dev);
int (*reset_prepare)(struct virtio_device *dev);