regr
static void aten_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
int r = regr + cont_map[cont] + 0x80;
static int aten_read_regr(struct pi_adapter *pi, int cont, int regr)
r = regr + cont_map[cont] + 0x40;
static int bpck_read_regr(struct pi_adapter *pi, int cont, int regr)
r = regr + cont_map[cont];
static void bpck_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
r = regr + cont_map[cont];
static int comm_read_regr(struct pi_adapter *pi, int cont, int regr)
r = regr + cont_map[cont];
static void comm_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
int r = regr + cont_map[cont];
static int dstr_read_regr(struct pi_adapter *pi, int cont, int regr)
r = regr + cont_map[cont];
static void dstr_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
int r = regr + cont_map[cont];
static void epat_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
int r = regr + cont_map[cont];
static int epat_read_regr(struct pi_adapter *pi, int cont, int regr)
r = regr + cont_map[cont];
static int epia_read_regr(struct pi_adapter *pi, int cont, int regr)
regr += cont_map[cont];
r = regr ^ 0x39;
r = regr ^ 0x31;
r = regr^0x29;
w3(regr); w2(0x24); a = r4(); w2(4);
static void epia_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
regr += cont_map[cont];
r = regr ^ 0x19;
r = regr ^ 0x40;
static void fit2_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
w2(0xc); w0(regr); w2(4); w0(val); w2(5); w0(0); w2(4);
static int fit2_read_regr(struct pi_adapter *pi, int cont, int regr)
if (regr != 6)
r = regr + 0x10;
static void fit3_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
regr += cont << 3;
w2(0xc); w0(regr); w2(0x8); w2(0xc);
w2(0xc); w0(regr); w2(0x8); w2(0xc);
static int fit3_read_regr(struct pi_adapter *pi, int cont, int regr)
regr += cont << 3;
w2(0xc); w0(regr + 0x10); w2(0x8); w2(0xc);
w2(0xc); w0(regr + 0x90); w2(0x8); w2(0xc);
w2(0xc); w0(regr + 0x90); w2(0x8); w2(0xc);
CMD(regr + 0x80);
CMD(regr + 0x80);
static int friq_read_regr(struct pi_adapter *pi, int cont, int regr)
r = regr + cont_map[cont];
static void friq_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
int r = regr + cont_map[cont];
static void friq_read_block_int(struct pi_adapter *pi, char *buf, int count, int regr)
CMD(regr);
CMD(regr + 0xc0);
CMD(regr + 0x80);
w2(4); w0(regr + 0x80); cec4;
w2(4); w0(regr + 0x80); cec4;
static int frpw_read_regr(struct pi_adapter *pi, int cont, int regr)
r = regr + cont_map[cont];
static void frpw_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
int r = regr + cont_map[cont];
int regr)
w2(4); w0(regr); cec4;
w2(4); w0(regr + 0xc0); cec4;
w2(4); w0(regr + 0x80); cec4;
w2(4); w0(regr + 0x80); cec4;
static int kbic_read_regr(struct pi_adapter *pi, int cont, int regr)
w0(regr | 0x18 | s); w2(4); w2(6); w2(4); w2(1); w0(8);
w0(regr|0x38 | s); w2(4); w2(6); w2(4); w2(5); w0(8);
w0(regr | 0x08 | s); w2(4); w2(6); w2(4); w2(0xa5); w2(0xa1);
w0(0x20 | s); w2(4); w2(6); w2(4); w3(regr);
static void kbic_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
w0(regr | 0x10 | s); w2(4); w2(6); w2(4);
w0(0x20 | s); w2(4); w2(6); w2(4); w3(regr);
static void ktti_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
int r = regr + cont_map[cont];
static int ktti_read_regr(struct pi_adapter *pi, int cont, int regr)
r = regr + cont_map[cont];
static int on20_read_regr(struct pi_adapter *pi, int cont, int regr)
r = (regr << 2) + 1 + cont;
static void on20_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
int r = (regr << 2) + 1 + cont;
static int on26_read_regr(struct pi_adapter *pi, int cont, int regr)
r = (regr << 2) + 1 + cont;
static void on26_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
int r = (regr << 2) + 1 + cont;
void (*write_regr)(struct pi_adapter *pi, int cont, int regr, int val);
int (*read_regr)(struct pi_adapter *pi, int cont, int regr);
value = regr(reg);
return (regr(vpifregs[channel_id].ch_ctrl) & VPIF_CH_FID_MASK)
regw((regr(reg)) | (0x01 << bit), reg);
regw(((regr(reg)) & ~(0x01 << bit)), reg);
#define channel0_intr_assert() (regw((regr(VPIF_CH0_CTRL)|\
#define channel1_intr_assert() (regw((regr(VPIF_CH1_CTRL)|\
#define channel2_intr_assert() (regw((regr(VPIF_CH2_CTRL)|\
#define channel3_intr_assert() (regw((regr(VPIF_CH3_CTRL)|\
regw((regr(VPIF_CH0_CTRL) | (VPIF_CH0_EN)), VPIF_CH0_CTRL);
regw((regr(VPIF_CH0_CTRL) & (~VPIF_CH0_EN)), VPIF_CH0_CTRL);
regw((regr(VPIF_CH1_CTRL) | (VPIF_CH1_EN)), VPIF_CH1_CTRL);
regw((regr(VPIF_CH1_CTRL) & (~VPIF_CH1_EN)), VPIF_CH1_CTRL);
regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN);
regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET);
regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH0), VPIF_INTEN);
regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH0),
regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH0)), VPIF_INTEN);
regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH0),
regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN);
regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET);
regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH1), VPIF_INTEN);
regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH1),
regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH1)), VPIF_INTEN);
regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH1),
regw((regr(VPIF_CH2_CTRL) | (VPIF_CH2_CLK_EN)), VPIF_CH2_CTRL);
regw((regr(VPIF_CH2_CTRL) | (VPIF_CH2_EN)), VPIF_CH2_CTRL);
regw((regr(VPIF_CH2_CTRL) & (~VPIF_CH2_CLK_EN)), VPIF_CH2_CTRL);
regw((regr(VPIF_CH2_CTRL) & (~VPIF_CH2_EN)), VPIF_CH2_CTRL);
regw((regr(VPIF_CH3_CTRL) | (VPIF_CH3_CLK_EN)), VPIF_CH3_CTRL);
regw((regr(VPIF_CH3_CTRL) | (VPIF_CH3_EN)), VPIF_CH3_CTRL);
regw((regr(VPIF_CH3_CTRL) & (~VPIF_CH3_CLK_EN)), VPIF_CH3_CTRL);
regw((regr(VPIF_CH3_CTRL) & (~VPIF_CH3_EN)), VPIF_CH3_CTRL);
regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN);
regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET);
regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH2), VPIF_INTEN);
regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH2),
regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH2)), VPIF_INTEN);
regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH2),
regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN);
regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET);
regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH3), VPIF_INTEN);
regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH3),
regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH3)), VPIF_INTEN);
regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH3),
status = regr(VPIF_STATUS) & mask;