regmap_update_bits_async
regmap_update_bits_async(lp->regmap_dar, DAR_PHY_CTRL1,
regmap_update_bits_async(lp->regmap_dar, DAR_PHY_CTRL1,
regmap_update_bits_async(arizona->regmap,
regmap_update_bits_async(arizona->regmap, ARIZONA_OUTPUT_ENABLES_1,
regmap_update_bits_async(arizona->regmap, base + ARIZONA_AIF_BCLK_CTRL,
regmap_update_bits_async(arizona->regmap, base + ARIZONA_AIF_TX_PIN_CTRL,
regmap_update_bits_async(arizona->regmap,
regmap_update_bits_async(arizona->regmap,
regmap_update_bits_async(arizona->regmap,
regmap_update_bits_async(arizona->regmap,
regmap_update_bits_async(arizona->regmap,
regmap_update_bits_async(arizona->regmap,
regmap_update_bits_async(arizona->regmap,
regmap_update_bits_async(arizona->regmap, base + 3,
regmap_update_bits_async(arizona->regmap, base + 4,
regmap_update_bits_async(arizona->regmap, base + 5,
regmap_update_bits_async(arizona->regmap, base + 6,
regmap_update_bits_async(arizona->regmap, base + 2,
regmap_update_bits_async(fll->arizona->regmap, fll->base + 0x9,
regmap_update_bits_async(arizona->regmap, fll->base + 0x11,
regmap_update_bits_async(arizona->regmap, fll->base + 0x17,
regmap_update_bits_async(arizona->regmap, fll->base + 0x17,
regmap_update_bits_async(arizona->regmap, fll->base + 0x11,
regmap_update_bits_async(arizona->regmap, fll->base + 1,
regmap_update_bits_async(arizona->regmap, fll->base + 1,
regmap_update_bits_async(arizona->regmap, fll->base + 1,
regmap_update_bits_async(arizona->regmap, fll->base + 1,
regmap_update_bits_async(arizona->regmap,
regmap_update_bits_async(regmap,
regmap_update_bits_async(regmap,
regmap_update_bits_async(regmap,