drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1453

struct atom_mc_reg_table *reg_table)

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1461

memset(reg_table, 0, sizeof(struct atom_mc_reg_table));

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1490

reg_table->mc_reg_address[i].s1 =

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1492

reg_table->mc_reg_address[i].pre_reg_data =

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1498

reg_table->last = i;

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1504

reg_table->mc_reg_table_entry[num_ranges].mclk_max =

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1507

for (i = 0, j = 1; i < reg_table->last; i++) {

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1508

if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1509

reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1512

} else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1515

reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1516

reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1526

reg_table->num_entries = num_ranges;

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h

180

struct atom_mc_reg_table *reg_table);

drivers/gpu/drm/i915/i915_cmd_parser.c

840

const struct drm_i915_reg_descriptor *reg_table,

drivers/gpu/drm/i915/i915_cmd_parser.c

848

u32 curr = i915_mmio_reg_offset(reg_table[i].addr);

drivers/gpu/drm/radeon/radeon.h

347

struct atom_mc_reg_table *reg_table);

drivers/gpu/drm/radeon/radeon_atombios.c

3975

struct atom_mc_reg_table *reg_table)

drivers/gpu/drm/radeon/radeon_atombios.c

3983

memset(reg_table, 0, sizeof(struct atom_mc_reg_table));

drivers/gpu/drm/radeon/radeon_atombios.c

4012

reg_table->mc_reg_address[i].s1 =

drivers/gpu/drm/radeon/radeon_atombios.c

4014

reg_table->mc_reg_address[i].pre_reg_data =

drivers/gpu/drm/radeon/radeon_atombios.c

4020

reg_table->last = i;

drivers/gpu/drm/radeon/radeon_atombios.c

4026

reg_table->mc_reg_table_entry[num_ranges].mclk_max =

drivers/gpu/drm/radeon/radeon_atombios.c

4029

for (i = 0, j = 1; i < reg_table->last; i++) {

drivers/gpu/drm/radeon/radeon_atombios.c

4030

if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {

drivers/gpu/drm/radeon/radeon_atombios.c

4031

reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =

drivers/gpu/drm/radeon/radeon_atombios.c

4034

} else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {

drivers/gpu/drm/radeon/radeon_atombios.c

4035

reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =

drivers/gpu/drm/radeon/radeon_atombios.c

4036

reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];

drivers/gpu/drm/radeon/radeon_atombios.c

4046

reg_table->num_entries = num_ranges;

drivers/hv/mshv_vtl_main.c

513

} reg_table[] = {

drivers/hv/mshv_vtl_main.c

578

for (i = 0; i < ARRAY_SIZE(reg_table); i++) {

drivers/hv/mshv_vtl_main.c

579

if (reg_table[i].reg_name != gpr_name)

drivers/hv/mshv_vtl_main.c

581

if (reg_table[i].debug_reg_num != -1) {

drivers/hv/mshv_vtl_main.c

587

native_set_debugreg(reg_table[i].debug_reg_num, *reg64);

drivers/hv/mshv_vtl_main.c

589

*reg64 = native_get_debugreg(reg_table[i].debug_reg_num);

drivers/hv/mshv_vtl_main.c

593

wrmsrl(reg_table[i].msr_addr, *reg64);

drivers/hv/mshv_vtl_main.c

595

rdmsrl(reg_table[i].msr_addr, *reg64);

drivers/media/i2c/imx214.c

1159

ret = cci_multi_reg_write(imx214->regmap, mode->reg_table,

drivers/media/i2c/imx214.c

506

const struct cci_reg_sequence *reg_table;

drivers/media/i2c/imx214.c

513

.reg_table = mode_4096x2304,

drivers/media/i2c/imx214.c

520

.reg_table = mode_1920x1080,

drivers/net/wireless/mediatek/mt7601u/phy.c

291

const struct reg_table *t;

drivers/net/wireless/mediatek/mt7601u/phy.c

303

const struct reg_table *t;

sound/soc/codecs/mt6660.c

230

static const struct reg_table mt6660_setting_table[] = {