arch/alpha/lib/stacktrace.c

40

static char reg_name[][4] = {

arch/alpha/lib/stacktrace.c

62

printk("\t\t%s / 0x%016lx\n", reg_name[reg], value);

drivers/accel/amdxdna/aie2_pci.h

220

#define DEFINE_BAR_OFFSET(reg_name, bar, reg_addr) \

drivers/accel/amdxdna/aie2_pci.h

221

[reg_name] = {bar##_BAR_INDEX, (reg_addr) - bar##_BAR_BASE}

drivers/accel/ivpu/ivpu_hw_reg_io.h

64

const char *func_name, const char *reg_name, const char *fld_name)

drivers/accel/ivpu/ivpu_hw_reg_io.h

70

func_name, reg_name, reg_offset, fld_name, exp_masked_val);

drivers/accel/ivpu/ivpu_hw_reg_io.h

81

func_name, reg_name, reg_offset, fld_name, ret ? "ETIMEDOUT" : "OK", reg_val);

drivers/char/hw_random/cctrng.c

26

#define CC_REG_FLD_GET(reg_name, fld_name, reg_val) \

drivers/char/hw_random/cctrng.c

27

(FIELD_GET(CC_GENMASK(CC_ ## reg_name ## _ ## fld_name), reg_val))

drivers/clk/clk-si5341.c

1594

char reg_name[10];

drivers/clk/clk-si5341.c

1596

snprintf(reg_name, sizeof(reg_name), "vddo%d", i);

drivers/clk/clk-si5341.c

1598

&client->dev, reg_name);

drivers/clk/clk-si5341.c

1610

reg_name, err);

drivers/cpufreq/cpufreq-dt.c

161

const char *reg_name[] = { NULL, NULL };

drivers/cpufreq/cpufreq-dt.c

186

reg_name[0] = find_supply_name(cpu_dev);

drivers/cpufreq/cpufreq-dt.c

187

if (reg_name[0]) {

drivers/cpufreq/cpufreq-dt.c

188

priv->opp_token = dev_pm_opp_set_regulators(cpu_dev, reg_name);

drivers/crypto/ccree/cc_driver.h

94

#define CC_REG(reg_name) CC_ ## reg_name ## _REG_OFFSET

drivers/edac/imh_base.c

62

#define DEFINE_LOCAL_REG(name, cfg, package, north, ip_name, ip_idx, reg_name) \

drivers/edac/imh_base.c

70

.offset = (cfg)->ip_name##_reg_##reg_name##_offset, \

drivers/edac/imh_base.c

71

.width = (cfg)->ip_name##_reg_##reg_name##_width, \

drivers/gpu/drm/amd/amdgpu/amdgpu.h

1301

uint32_t inst, uint32_t reg_addr, char reg_name[],

drivers/gpu/drm/amd/amdgpu/amdgpu.h

147

const char *reg_name;

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

7616

uint32_t inst, uint32_t reg_addr, char reg_name[],

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

7636

inst, reg_name, (uint32_t)expected_value,

drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c

537

drm_printf(p, "%-50s \t 0x%08x\n", adev->jpeg.reg_list[j].reg_name,

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c

1633

drm_printf(p, "%-50s \t 0x%08x\n", adev->vcn.reg_list[j].reg_name,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

9650

gc_reg_list_10_1[i].reg_name,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

9674

gc_cp_reg_list_10[reg].reg_name,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

9699

gc_gfx_queue_reg_list_10[reg].reg_name,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

7034

gc_reg_list_11_0[i].reg_name,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

7058

gc_cp_reg_list_11[reg].reg_name,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

7083

gc_gfx_queue_reg_list_11[reg].reg_name,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

5108

gc_reg_list_12_0[i].reg_name,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

5127

gc_cp_reg_list_12[reg].reg_name,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

5152

gc_gfx_queue_reg_list_12[reg].reg_name,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

7346

gc_reg_list_9[i].reg_name,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

7370

gc_cp_reg_list_9[reg].reg_name,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4576

gc_reg_list_9_4_3[i].reg_name,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4615

gc_cp_reg_list_9_4_3[reg].reg_name,

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

2369

drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_4_0[j].reg_name,

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

2066

drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_4_4_2[j].reg_name,

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1876

drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_5_0[j].reg_name,

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1878

drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_5_2[j].reg_name,

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

1714

drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_6_0[j].reg_name,

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

1646

drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_7_0[j].reg_name,

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

1575

drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_7_1[j].reg_name,

drivers/gpu/drm/amd/amdgpu/soc15_common.h

58

#define WREG32_FIELD15_PREREG(ip, idx, reg_name, field, val) \

drivers/gpu/drm/amd/amdgpu/soc15_common.h

59

__WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][reg##reg_name##_BASE_IDX] + reg##reg_name, \

drivers/gpu/drm/amd/amdgpu/soc15_common.h

61

adev->reg_offset[ip##_HWIP][idx][reg##reg_name##_BASE_IDX] + reg##reg_name, \

drivers/gpu/drm/amd/amdgpu/soc15_common.h

63

~REG_FIELD_MASK(reg_name, field)) | (val) << REG_FIELD_SHIFT(reg_name, field), \

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

1992

drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_1_0[j].reg_name,

drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c

54

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

50

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

35

#define SR(reg_name)\

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

36

.reg_name = mm ## reg_name

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

39

#define SRI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

40

.reg_name = mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

37

#define SR(reg_name)\

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

38

.reg_name = mm ## reg_name

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

41

#define SRI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

42

.reg_name = mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c

50

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c

54

#define SR(reg_name)\

drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c

55

.reg_name = mm ## reg_name

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c

64

#define REG(reg_name) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c

65

(MP1_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c

67

#define FN(reg_name, field) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c

68

FD(reg_name##__##field)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

43

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

53

#define SR(reg_name)\

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

54

.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

55

mm ## reg_name

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

49

#define SR(reg_name)\

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

50

.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

51

mm ## reg_name

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

57

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

50

#define REG(reg_name) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

51

(CLK_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

40

#define REG(reg_name) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

41

(MP0_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

43

#define FN(reg_name, field) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

44

FD(reg_name##__##field)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

49

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

59

#define SR(reg_name)\

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

60

.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

61

mm ## reg_name

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

64

#define CLK_SRI(reg_name, block, inst)\

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

65

.reg_name = mm ## block ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

39

#define REG(reg_name) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

40

mm ## reg_name

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.c

38

#define REG(reg_name) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.c

39

mm ## reg_name

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

39

#define REG(reg_name) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

40

(MP0_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

42

#define FN(reg_name, field) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

43

FD(reg_name##__##field)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

58

#define REG(reg_name) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

59

(CLK_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

70

#define REG(reg_name) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

71

(CLK_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

36

#define REG(reg_name) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

37

(MP0_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

39

#define FN(reg_name, field) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

40

FD(reg_name##__##field)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

104

#define REG(reg_name) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

105

(CLK_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

53

#define REG(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

55

#define FN(reg_name, field) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

56

FD(reg_name##__##field)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

61

#define REG(reg_name) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

62

(MP0_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

64

#define FN(reg_name, field) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

65

FD(reg_name##__##field)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

53

#define REG(reg_name) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

54

(MP0_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

56

#define FN(reg_name, field) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

57

FD(reg_name##__##field)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

100

.reg_name = mm ## reg_name

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

115

#define CLK_SR_DCN321(reg_name, block, inst)\

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

116

.reg_name = mm ## block ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

85

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

95

#define SR(reg_name)\

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

96

.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

97

reg ## reg_name

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

99

#define CLK_SR_DCN32(reg_name)\

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

37

#define REG(reg_name) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

38

mm ## reg_name

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn351_clk_mgr.c

103

#define SR(reg_name)\

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn351_clk_mgr.c

104

.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn351_clk_mgr.c

105

reg ## reg_name

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn351_clk_mgr.c

107

#define CLK_SR_DCN35(reg_name)\

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn351_clk_mgr.c

108

.reg_name = mm ## reg_name

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

124

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

134

#define SR(reg_name)\

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

135

.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

136

reg ## reg_name

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

138

#define CLK_SR_DCN35(reg_name)\

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

139

.reg_name = mm ## reg_name

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

53

#define REG(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

55

#define FN(reg_name, field) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

56

FD(reg_name##__##field)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

43

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

53

#define SR(reg_name)\

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

54

.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

55

reg ## reg_name

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

57

#define CLK_SR_DCN401(reg_name, block, inst)\

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

58

.reg_name = mm ## block ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

17

#define REG(reg_name) \

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

18

mm ## reg_name

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

39

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

56

#define DCCG_SF(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

57

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

59

#define DCCG_SFI(reg_name, field_name, field_prefix, inst, post_fix)\

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

60

.field_prefix ## _ ## field_name[inst] = reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

62

#define DCCG_SFII(block, reg_name, field_prefix, field_name, inst, post_fix)\

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

63

.field_prefix ## _ ## field_name[inst] = block ## inst ## _ ## reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c

39

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

38

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c

37

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c

37

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

39

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

41

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h

32

#define DCCG_SFII(block, reg_name, field_prefix, field_name, inst, post_fix)\

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h

33

.field_prefix ## _ ## field_name[inst] = block ## inst ## _ ## reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

38

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h

31

#define DCCG_SFII(block, reg_name, field_prefix, field_name, inst, post_fix)\

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h

32

.field_prefix ## _ ## field_name[inst] = block ## inst ## _ ## reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

38

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

30

#define DCCG_SFII(block, reg_name, field_prefix, field_name, inst, post_fix)\

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

31

.field_prefix ## _ ## field_name[inst] = block ## inst ## _ ## reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

48

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

31

#define DCCG_SFII(block, reg_name, field_prefix, field_name, inst, post_fix)\

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

32

.field_prefix ## _ ## field_name[inst] = block ## inst ## _ ## reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/dce/dce_abm.c

44

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dce/dce_abm.h

131

#define ABM_SF(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/dce/dce_abm.h

132

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/dce/dce_audio.c

43

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dce/dce_audio.c

49

#define AZ_REG_READ(reg_name) \

drivers/gpu/drm/amd/display/dc/dce/dce_audio.c

50

read_indirect_azalia_reg(audio, IX_REG(reg_name))

drivers/gpu/drm/amd/display/dc/dce/dce_audio.c

52

#define AZ_REG_WRITE(reg_name, value) \

drivers/gpu/drm/amd/display/dc/dce/dce_audio.c

53

write_indirect_azalia_reg(audio, IX_REG(reg_name), value)

drivers/gpu/drm/amd/display/dc/dce/dce_audio.h

44

#define SF(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/dce/dce_audio.h

45

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

36

#define REG(reg_name)\

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

37

(aux110->regs->reg_name)

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

50

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dce/dce_aux.h

212

#define AUX_SF(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/dce/dce_aux.h

213

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c

42

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

53

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h

45

#define CS_SF(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h

46

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

41

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h

100

#define DMCU_SF(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h

101

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c

37

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

103

#define I2C_SF(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

104

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c

34

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h

64

#define IPP_SF(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h

65

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

36

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h

154

#define SFB(blk_name, reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h

155

.field_name = blk_name ## reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/dce/dce_opp.c

37

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dce/dce_opp.h

95

#define OPP_SF(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/dce/dce_opp.h

96

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c

46

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h

32

#define DCE_PANEL_CNTL_SR(reg_name, block)\

drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h

33

.reg_name = mm ## block ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h

45

#define DCN_PANEL_CNTL_SR(reg_name, block)\

drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h

46

.reg_name = BASE(mm ## block ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h

47

mm ## block ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h

59

#define DCE_PANEL_CNTL_SF(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h

60

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

38

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

116

#define SE_SF(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

117

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

36

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dce/dce_transform.h

176

#define XFM_SF(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/dce/dce_transform.h

177

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

46

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

42

#define CRTC_REG_UPDATE_N(reg_name, n, ...) \

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

43

generic_reg_update_soc15(tg110->base.ctx, tg110->offsets.crtc, reg_name, n, __VA_ARGS__)

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

45

#define CRTC_REG_SET_N(reg_name, n, ...) \

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

46

generic_reg_set_soc15(tg110->base.ctx, tg110->offsets.crtc, reg_name, n, __VA_ARGS__)

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c

38

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c

39

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h

34

#define SR(reg_name)\

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h

35

.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h

36

mm ## reg_name

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h

38

#define SRI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h

39

.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h

40

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h

43

#define SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h

44

.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h

45

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h

47

#define SF(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h

48

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c

34

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h

76

#define IPP_SF(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h

77

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

42

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c

43

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c

38

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c

46

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dcn201/dcn201_mpc.c

39

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dcn201/dcn201_opp.c

34

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dcn201/dcn201_opp.h

33

#define OPP_SF(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/dcn201/dcn201_opp.h

34

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c

47

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_afmt.c

39

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c

40

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

40

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c

38

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c

45

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dcn301/dcn301_panel_cntl.h

42

#define DCN301_PANEL_CNTL_SF(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/dcn301/dcn301_panel_cntl.h

43

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_afmt.c

40

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_apg.c

39

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.c

39

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_dio.c

16

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

1378

#define HPD_REG_READ(reg_name) \

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

1379

dm_read_reg(CTX, HPD_REG(reg_name))

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

1381

#define HPD_REG_UPDATE_N(reg_name, n, ...) \

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

1383

HPD_REG(reg_name), \

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

1386

#define HPD_REG_UPDATE(reg_name, field, val) \

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

1387

HPD_REG_UPDATE_N(reg_name, 1, \

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

1388

FN(reg_name, field), val)

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

1409

#define AUX_REG_READ(reg_name) \

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

1410

dm_read_reg(CTX, AUX_REG(reg_name))

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

1412

#define AUX_REG_UPDATE_N(reg_name, n, ...) \

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

1414

AUX_REG(reg_name), \

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

1417

#define AUX_REG_UPDATE(reg_name, field, val) \

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

1418

AUX_REG_UPDATE_N(reg_name, 1, \

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

1419

FN(reg_name, field), val)

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

45

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

176

#define LE_SF(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

177

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

42

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

196

#define SE_SF(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

197

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c

303

#define AUX_REG_READ(reg_name) \

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c

304

dm_read_reg(CTX, AUX_REG(reg_name))

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c

306

#define AUX_REG_WRITE(reg_name, val) \

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c

307

dm_write_reg(CTX, AUX_REG(reg_name), val)

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c

45

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

42

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c

214

#define AUX_REG_READ(reg_name) \

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c

215

dm_read_reg(CTX, AUX_REG(reg_name))

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c

217

#define AUX_REG_WRITE(reg_name, val) \

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c

218

dm_write_reg(CTX, AUX_REG(reg_name), val)

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c

44

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

40

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c

44

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

51

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

60

#define AUX_REG_READ(reg_name) \

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

61

dm_read_reg(CTX, AUX_REG(reg_name))

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

63

#define AUX_REG_WRITE(reg_name, val) \

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

64

dm_write_reg(CTX, AUX_REG(reg_name), val)

drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

43

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c

53

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c

59

#define AUX_REG_READ(reg_name) \

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c

60

dm_read_reg(CTX, AUX_REG(reg_name))

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c

62

#define AUX_REG_WRITE(reg_name, val) \

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c

63

dm_write_reg(CTX, AUX_REG(reg_name), val)

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

42

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c

50

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c

56

#define AUX_REG_READ(reg_name) \

drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c

57

dm_read_reg(CTX, AUX_REG(reg_name))

drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c

59

#define AUX_REG_WRITE(reg_name, val) \

drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c

60

dm_write_reg(CTX, AUX_REG(reg_name), val)

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

41

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

42

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c

52

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c

58

#define AUX_REG_READ(reg_name) \

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c

59

dm_read_reg(CTX, AUX_REG(reg_name))

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c

61

#define AUX_REG_WRITE(reg_name, val) \

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c

62

dm_write_reg(CTX, AUX_REG(reg_name), val)

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

45

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dm_services.h

100

reg_name ## __ ## reg_field ## __SHIFT)

drivers/gpu/drm/amd/display/dc/dm_services.h

112

#define set_reg_field_value(reg_value, value, reg_name, reg_field)\

drivers/gpu/drm/amd/display/dc/dm_services.h

116

reg_name ## __ ## reg_field ## _MASK,\

drivers/gpu/drm/amd/display/dc/dm_services.h

117

reg_name ## __ ## reg_field ## __SHIFT)

drivers/gpu/drm/amd/display/dc/dm_services.h

157

#define generic_reg_update_soc15(ctx, inst_offset, reg_name, n, ...)\

drivers/gpu/drm/amd/display/dc/dm_services.h

158

generic_reg_update_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name + inst_offset, \

drivers/gpu/drm/amd/display/dc/dm_services.h

161

#define generic_reg_set_soc15(ctx, inst_offset, reg_name, n, ...)\

drivers/gpu/drm/amd/display/dc/dm_services.h

162

generic_reg_set_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name + inst_offset, 0, \

drivers/gpu/drm/amd/display/dc/dm_services.h

165

#define get_reg_field_value_soc15(reg_value, block, reg_num, reg_name, reg_field)\

drivers/gpu/drm/amd/display/dc/dm_services.h

168

block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\

drivers/gpu/drm/amd/display/dc/dm_services.h

169

block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT)

drivers/gpu/drm/amd/display/dc/dm_services.h

171

#define set_reg_field_value_soc15(reg_value, value, block, reg_num, reg_name, reg_field)\

drivers/gpu/drm/amd/display/dc/dm_services.h

175

block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\

drivers/gpu/drm/amd/display/dc/dm_services.h

176

block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT)

drivers/gpu/drm/amd/display/dc/dm_services.h

96

#define get_reg_field_value(reg_value, reg_name, reg_field)\

drivers/gpu/drm/amd/display/dc/dm_services.h

99

reg_name ## __ ## reg_field ## _MASK,\

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

43

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

48

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

37

#define TF_SF(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

38

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

41

#define TF2_SF(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

42

.field_name = reg_name ## _ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

49

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

50

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

48

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

46

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

41

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

40

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

40

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

36

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

42

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

49

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

50

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

56

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

87

#define DSC_SF(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

88

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

91

#define DSC2_SF(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

92

.field_name = reg_name ## _ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

54

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

40

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

40

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

43

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/dwb/dcn35/dcn35_dwb.c

34

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c

42

#define SF_HPD(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c

43

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c

45

#define REG(reg_name)\

drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c

46

mm ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c

48

#define REGI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c

49

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c

79

#define SF_DDC(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c

80

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c

46

#define SF_HPD(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c

47

.field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c

50

#define SF_HPD(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c

51

.field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c

60

#define REG(reg_name)\

drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c

61

BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c

63

#define REGI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c

64

BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c

65

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c

96

#define SF_DDC(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c

97

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

51

#define REG(reg_name)\

drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

52

BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

54

#define REGI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

55

BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

56

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c

41

#define REG(reg_name)\

drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c

42

mm ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c

83

#define SF_DDC(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c

84

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c

41

#define REG(reg_name)\

drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c

42

mm ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c

83

#define SF_DDC(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c

84

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c

128

#define SF_GENERIC(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c

129

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c

47

#define SF_HPD(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c

48

.field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c

57

#define REG(reg_name)\

drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c

58

BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c

60

#define REGI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c

61

BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c

62

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c

92

#define SF_DDC(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c

93

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

51

#define REG(reg_name)\

drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

52

BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

54

#define REGI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

55

BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

56

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

102

#define SF_DDC(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

103

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

158

#define SF_GENERIC(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

159

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

59

#define REG(reg_name)\

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

60

BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

62

#define SF_HPD(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

63

.field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

65

#define REGI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

66

BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

67

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

69

#define SF(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

70

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

55

#define REG(reg_name)\

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

56

BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

57

#define SF_HPD(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

58

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c

100

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c

139

#define SF_GENERIC(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c

140

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c

57

#define REG(reg_name)\

drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c

58

BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c

60

#define SF_HPD(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c

61

.field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c

63

#define REGI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c

64

BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c

65

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c

67

#define SF(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c

68

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c

99

#define SF_DDC(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

55

#define REG(reg_name)\

drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

56

BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

57

#define SF_HPD(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

58

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

109

#define SF_DDC(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

110

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

165

#define SF_GENERIC(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

166

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

66

#define REG(reg_name)\

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

67

BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

69

#define SF_HPD(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

70

.field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

72

#define REGI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

73

BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

74

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

76

#define SF(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

77

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

60

#define REG(reg_name)\

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

61

BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

62

#define SF_HPD(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

63

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c

105

#define SF_DDC(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c

106

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c

157

#define SF_GENERIC(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c

158

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c

63

#define REG(reg_name)\

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c

64

BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c

66

#define SF_HPD(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c

67

.field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c

69

#define REGI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c

70

BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c

71

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c

73

#define SF(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c

74

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

55

#define REG(reg_name)\

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

56

BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

57

#define SF_HPD(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

58

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

101

#define SF_DDC(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

102

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

169

#define SF_GENERIC(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

170

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

59

#define REG(reg_name)\

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

60

BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

62

#define SF_HPD(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

63

.field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

65

#define REGI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

66

BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

67

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

69

#define SF(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

70

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

53

#define REG(reg_name)\

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

54

BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

55

#define SF_HPD(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

56

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c

161

#define SF_GENERIC(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c

162

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c

39

#define REG(reg_name)\

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c

40

BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c

42

#define SF_HPD(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c

43

.field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c

45

#define REGI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c

46

BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c

47

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c

49

#define SF(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c

50

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c

81

#define SF_DDC(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c

82

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

28

#define REG(reg_name)\

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

29

BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

30

#define SF_HPD(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

31

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c

38

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c

39

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c

34

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c

37

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

38

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

38

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/hpo/dcn32/dcn32_hpo_dp_link_encoder.c

38

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

39

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

231

#define HUBBUB_SF(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

232

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

38

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

48

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/hubbub/dcn201/dcn201_hubbub.c

40

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/hubbub/dcn201/dcn201_hubbub.c

50

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

39

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

49

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

40

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/hubbub/dcn301/dcn301_hubbub.c

37

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/hubbub/dcn301/dcn301_hubbub.c

47

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

41

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

42

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

44

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

41

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

38

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

270

#define HUBP_SF(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

271

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

44

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

39

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

45

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

42

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

39

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

39

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

37

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

40

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c

37

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

705

#define HWS_SF(blk_name, reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

706

.field_name = blk_name ## reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

708

#define HWS_SF1(blk_name, reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

709

.field_name = blk_name ## reg_name ## __ ## blk_name ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

97

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

47

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

73

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

72

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

56

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

49

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

72

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_hwseq.c

39

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

41

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_hwseq.c

42

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

69

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

69

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

67

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

75

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

55

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

115

#define CLK_SF(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

116

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

84

#define CLK_SRI(reg_name, block, inst)\

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

85

.reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

86

mm ## block ## _ ## inst ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

156

#define REG_GET(reg_name, field, val) \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

157

generic_reg_get(CTX, REG(reg_name), \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

158

FN(reg_name, field), val)

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

160

#define REG_GET_2(reg_name, f1, v1, f2, v2) \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

161

generic_reg_get2(CTX, REG(reg_name), \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

162

FN(reg_name, f1), v1, \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

163

FN(reg_name, f2), v2)

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

165

#define REG_GET_3(reg_name, f1, v1, f2, v2, f3, v3) \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

166

generic_reg_get3(CTX, REG(reg_name), \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

167

FN(reg_name, f1), v1, \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

168

FN(reg_name, f2), v2, \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

169

FN(reg_name, f3), v3)

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

171

#define REG_GET_4(reg_name, f1, v1, f2, v2, f3, v3, f4, v4) \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

172

generic_reg_get4(CTX, REG(reg_name), \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

173

FN(reg_name, f1), v1, \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

174

FN(reg_name, f2), v2, \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

175

FN(reg_name, f3), v3, \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

176

FN(reg_name, f4), v4)

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

178

#define REG_GET_5(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

179

generic_reg_get5(CTX, REG(reg_name), \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

180

FN(reg_name, f1), v1, \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

181

FN(reg_name, f2), v2, \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

182

FN(reg_name, f3), v3, \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

183

FN(reg_name, f4), v4, \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

184

FN(reg_name, f5), v5)

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

186

#define REG_GET_6(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

187

generic_reg_get6(CTX, REG(reg_name), \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

188

FN(reg_name, f1), v1, \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

189

FN(reg_name, f2), v2, \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

190

FN(reg_name, f3), v3, \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

191

FN(reg_name, f4), v4, \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

192

FN(reg_name, f5), v5, \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

193

FN(reg_name, f6), v6)

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

195

#define REG_GET_7(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

196

generic_reg_get7(CTX, REG(reg_name), \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

197

FN(reg_name, f1), v1, \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

198

FN(reg_name, f2), v2, \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

199

FN(reg_name, f3), v3, \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

200

FN(reg_name, f4), v4, \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

201

FN(reg_name, f5), v5, \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

202

FN(reg_name, f6), v6, \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

203

FN(reg_name, f7), v7)

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

205

#define REG_GET_8(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

206

generic_reg_get8(CTX, REG(reg_name), \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

207

FN(reg_name, f1), v1, \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

208

FN(reg_name, f2), v2, \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

209

FN(reg_name, f3), v3, \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

210

FN(reg_name, f4), v4, \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

211

FN(reg_name, f5), v5, \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

212

FN(reg_name, f6), v6, \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

213

FN(reg_name, f7), v7, \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

214

FN(reg_name, f8), v8)

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

218

#define REG_WAIT(reg_name, field, val, delay_between_poll_us, max_try) \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

220

REG(reg_name), FN(reg_name, field), val,\

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

225

#define REG_UPDATE_N(reg_name, n, ...) \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

227

REG(reg_name), \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

230

#define REG_UPDATE(reg_name, field, val) \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

231

REG_UPDATE_N(reg_name, 1, \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

232

FN(reg_name, field), val)

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

39

#define REG_READ(reg_name) \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

40

dm_read_reg(CTX, REG(reg_name))

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

42

#define REG_WRITE(reg_name, value) \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

43

dm_write_reg(CTX, REG(reg_name), value)

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

54

#define REG_SET_N(reg_name, n, initial_val, ...) \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

56

REG(reg_name), \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

60

#define FN(reg_name, field) \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

61

FD(reg_name##__##field)

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

63

#define REG_SET(reg_name, initial_val, field, val) \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

64

REG_SET_N(reg_name, 1, initial_val, \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

65

FN(reg_name, field), val)

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

71

#define SRI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

72

BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

73

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

168

#define SRI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

169

BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

170

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

171

#define SRI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

172

BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

173

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

121

#define SRI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

122

BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

123

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

178

#define SRI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

179

BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

180

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

182

#define SRI_DMUB(reg_name)\

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

183

BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

184

mm ## reg_name

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

185

#define SRI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

186

BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

187

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

189

#define SRI_DMUB(reg_name)\

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

190

BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

191

mm ## reg_name

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

170

#define SRI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

171

BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

172

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

174

#define SRI_DMUB(reg_name)\

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

175

BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

176

mm ## reg_name

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

116

#define SRI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

117

BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

118

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

173

#define SRI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

174

BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

175

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

177

#define SRI_DMUB(reg_name)\

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

178

BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

179

reg ## reg_name

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

175

#define SRI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

176

(BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

177

reg ## block ## id ## _ ## reg_name)

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

179

#define SRI_DMUB(reg_name)\

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

180

(BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

181

reg ## reg_name)

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

180

#define SRI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

181

BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

182

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

184

#define SRI_DMUB(reg_name)\

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

185

BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

186

reg ## reg_name

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

184

#define SRI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

185

BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

186

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

188

#define SRI_DMUB(reg_name)\

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

189

BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

190

reg ## reg_name

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

172

#define SRI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

173

BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

174

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

176

#define SRI_DMUB(reg_name)\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

177

BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

178

reg ## reg_name

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

151

#define SRI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

152

BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

153

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

155

#define SRI_DMUB(reg_name)\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

156

BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

157

reg ## reg_name

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

150

#define SRI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

151

BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

152

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

154

#define SRI_DMUB(reg_name)\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

155

BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

156

reg ## reg_name

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

164

#define SRI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

165

BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

166

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

168

#define SRI_DMUB(reg_name)\

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

169

BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

170

reg ## reg_name

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

40

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

40

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn35/dcn35_mmhubbub.c

37

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

36

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

43

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

40

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

38

#define SRII_MPC_RMU(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

39

.RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

40

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

41

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

40

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

35

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

33

#define OPP_SF(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

34

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c

35

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.h

33

#define OPP_SF(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.h

34

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/opp/dcn35/dcn35_opp.c

33

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

39

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

37

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

38

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

42

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c

42

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

40

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c

42

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

42

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

44

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

21

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

39

#define FN(reg_name, field_name) \

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

59

#define PG_CNTL_SF(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

60

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

137

#define SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

138

.reg_name = mm ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

141

#define SRI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

142

.reg_name = mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

505

#define SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

506

.reg_name[id] = mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

145

#define SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

146

.reg_name = mm ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

149

#define SRI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

150

.reg_name = mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

544

#define SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

545

.reg_name[id] = mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

146

#define SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

147

.reg_name = mm ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

150

#define SRI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

151

.reg_name = mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

525

#define SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

526

.reg_name[id] = mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

137

#define SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

138

.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

139

mm ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

141

#define SRI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

142

.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

143

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

152

#define MMHUB_SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

153

.reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

154

mm ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

784

#define SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

785

.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

786

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

154

#define SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

155

.reg_name = mm ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

158

#define SRI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

159

.reg_name = mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

623

#define SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

624

.reg_name[id] = mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

153

#define SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

154

.reg_name = mm ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

157

#define SRI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

158

.reg_name = mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

629

#define SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

630

.reg_name[id] = mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

113

#define SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

114

.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

115

mm ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

117

#define SRI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

118

.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

119

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

122

#define SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

123

.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

124

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

126

#define VUPDATE_SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

127

.reg_name[id] = BASE(mm ## reg_name ## 0 ## _ ## block ## id ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

128

mm ## reg_name ## 0 ## _ ## block ## id

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

131

#define SFRB(field_name, reg_name, bitfield, post_fix)\

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

132

.field_name = reg_name ## __ ## bitfield ## post_fix

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

141

#define NBIO_SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

142

.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

143

mm ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

152

#define MMHUB_SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

153

.reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

154

mm ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

129

#define SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

130

.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

131

mm ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

133

#define SRI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

134

.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

135

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

137

#define SRI2_DWB(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

138

.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

139

mm ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

140

#define SF_DWB(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

141

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

143

#define SF_DWB2(reg_name, block, id, field_name, post_fix) \

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

144

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

146

#define SRIR(var_name, reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

147

.var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

148

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

150

#define SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

151

.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

152

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

154

#define DCCG_SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

155

.block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

156

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

158

#define VUPDATE_SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

159

.reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

160

mm ## reg_name ## _ ## block ## id

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

169

#define NBIO_SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

170

.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

171

mm ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

180

#define MMHUB_SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

181

.reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

182

mmMM ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

252

#define SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

253

.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

254

mm ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

256

#define SRI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

257

.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

258

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

260

#define SRIR(var_name, reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

261

.var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

262

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

264

#define SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

265

.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

266

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

268

#define SRI_IX(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

269

.reg_name = ix ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

271

#define DCCG_SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

272

.block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

273

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

275

#define VUPDATE_SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

276

.reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

277

mm ## reg_name ## _ ## block ## id

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

286

#define NBIO_SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

287

.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

288

mm ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

297

#define MMHUB_SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

298

.reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

299

mmMM ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

102

#define SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

103

.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

104

mm ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

106

#define SRI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

107

.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

108

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

110

#define SRIR(var_name, reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

111

.var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

112

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

114

#define SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

115

.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

116

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

118

#define DCCG_SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

119

.block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

120

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

122

#define VUPDATE_SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

123

.reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

124

mm ## reg_name ## _ ## block ## id

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

133

#define NBIO_SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

134

.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

135

mm ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1368

#define REG(reg_name) \

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1369

(DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

144

#define MMHUB_SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

145

.reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

146

mmMM ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

118

#define SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

119

.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

120

mm ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

122

#define SRI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

123

.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

124

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

126

#define SRI2(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

127

.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

128

mm ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

130

#define SRIR(var_name, reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

131

.var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

132

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

134

#define SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

135

.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

136

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

138

#define SRII_MPC_RMU(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

139

.RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

140

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

142

#define SRII_DWB(reg_name, temp_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

143

.reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

146

#define SF_DWB2(reg_name, block, id, field_name, post_fix) \

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

147

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

149

#define DCCG_SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

150

.block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

151

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

153

#define VUPDATE_SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

154

.reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

155

mm ## reg_name ## _ ## block ## id

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

164

#define NBIO_SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

165

.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

166

mm ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

175

#define MMHUB_SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

176

.reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

177

mmMM ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

186

#define CLK_SRI(reg_name, block, inst)\

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

187

.reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

188

mm ## block ## _ ## inst ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2290

#define REG(reg_name) \

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2291

(DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

117

#define SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

118

.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

119

mm ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

121

#define SRI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

122

.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

123

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

125

#define SRI2(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

126

.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

127

mm ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

129

#define SRIR(var_name, reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

130

.var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

131

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

133

#define SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

134

.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

135

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

142

#define SRII_MPC_RMU(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

143

.RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

144

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

146

#define SRII_DWB(reg_name, temp_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

147

.reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

150

#define SF_DWB2(reg_name, block, id, field_name, post_fix) \

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

151

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

153

#define DCCG_SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

154

.block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

155

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

157

#define VUPDATE_SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

158

.reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

159

mm ## reg_name ## _ ## block ## id

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

168

#define NBIO_SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

169

.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

170

regBIF_BX0_ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

179

#define MMHUB_SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

180

.reg_name = MMHUB_BASE(regMM ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

181

regMM ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

190

#define CLK_SRI(reg_name, block, inst)\

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

191

.reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

192

mm ## block ## _ ## inst ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

949

#define REG(reg_name) \

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

950

(DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

171

#define NBIO_SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

172

.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

173

mm ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

180

#define SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

181

.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

183

#define SF(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

184

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

186

#define SRI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

187

.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

189

#define SRI2(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

190

.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

192

#define SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

193

.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

194

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

196

#define DCCG_SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

197

.block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

198

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

200

#define VUPDATE_SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

201

.reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

202

mm ## reg_name ## _ ## block ## id

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

204

#define SRII_DWB(reg_name, temp_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

205

.reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

208

#define SF_DWB2(reg_name, block, id, field_name, post_fix) \

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

209

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

211

#define SRII_MPC_RMU(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

212

.RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

213

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

167

#define NBIO_SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

168

.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

169

mm ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

176

#define SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

177

.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

179

#define SF(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

180

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

182

#define SRI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

183

.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

185

#define SRI2(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

186

.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

188

#define SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

189

.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

190

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

192

#define DCCG_SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

193

.block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

194

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

196

#define VUPDATE_SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

197

.reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

198

mm ## reg_name ## _ ## block ## id

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

200

#define SRII_DWB(reg_name, temp_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

201

.reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

204

#define SF_DWB2(reg_name, block, id, field_name, post_fix) \

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

205

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

207

#define SRII_MPC_RMU(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

208

.RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

209

mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

129

#define SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

130

.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

131

reg ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

133

#define SRI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

134

.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

135

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

137

#define SRI2(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

138

.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

139

reg ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

141

#define SRIR(var_name, reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

142

.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

143

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

145

#define SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

146

.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

147

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

149

#define SRII_MPC_RMU(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

150

.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

151

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

153

#define SRII_DWB(reg_name, temp_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

154

.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

157

#define SF_DWB2(reg_name, block, id, field_name, post_fix) \

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

158

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

160

#define DCCG_SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

161

.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

162

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

164

#define VUPDATE_SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

165

.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

166

reg ## reg_name ## _ ## block ## id

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

175

#define NBIO_SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

176

.reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

177

regBIF_BX1_ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

186

#define MMHUB_SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

187

.reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

188

mm ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

197

#define CLK_SRI(reg_name, block, inst)\

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

198

.reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

199

reg ## block ## _ ## inst ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

146

#define SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

147

.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

148

reg ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

150

#define SRI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

151

.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

152

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

154

#define SRI2(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

155

.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

156

reg ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

158

#define SRIR(var_name, reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

159

.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

160

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

162

#define SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

163

.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

164

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

166

#define SRII_MPC_RMU(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

167

.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

168

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

170

#define SRII_DWB(reg_name, temp_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

171

.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

174

#define SF_DWB2(reg_name, block, id, field_name, post_fix) \

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

175

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

177

#define DCCG_SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

178

.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

179

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

181

#define VUPDATE_SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

182

.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

183

reg ## reg_name ## _ ## block ## id

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

192

#define NBIO_SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

193

.reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

194

regBIF_BX2_ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

203

#define MMHUB_SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

204

.reg_name = MMHUB_BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

205

reg ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

214

#define CLK_SRI(reg_name, block, inst)\

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

215

.reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

216

reg ## block ## _ ## inst ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

163

#define SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

164

.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

165

reg ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

167

#define SRI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

168

.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

169

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

171

#define SRI2(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

172

.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

173

reg ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

175

#define SRIR(var_name, reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

176

.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

177

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

179

#define SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

180

.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

181

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

183

#define SRII_MPC_RMU(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

184

.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

185

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

187

#define SRII_DWB(reg_name, temp_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

188

.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

191

#define SF_DWB2(reg_name, block, id, field_name, post_fix) \

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

192

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

194

#define DCCG_SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

195

.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

196

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

198

#define VUPDATE_SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

199

.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

200

reg ## reg_name ## _ ## block ## id

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

209

#define NBIO_SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

210

.reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

211

regBIF_BX2_ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

149

#define SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

150

.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

151

reg ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

153

#define SRI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

154

.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

155

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

157

#define SRI2(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

158

.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

159

reg ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

161

#define SRIR(var_name, reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

162

.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

163

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

165

#define SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

166

.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

167

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

169

#define SRII_MPC_RMU(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

170

.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

171

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

173

#define SRII_DWB(reg_name, temp_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

174

.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

177

#define SF_DWB2(reg_name, block, id, field_name, post_fix) \

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

178

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

180

#define DCCG_SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

181

.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

182

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

184

#define VUPDATE_SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

185

.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

186

reg ## reg_name ## _ ## block ## id

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

195

#define NBIO_SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

196

.reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

197

regBIF_BX1_ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

118

#define SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

119

REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

120

reg ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

121

#define SR_ARR(reg_name, id) \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

122

REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

124

#define SR_ARR_INIT(reg_name, id, value) \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

125

REG_STRUCT[id].reg_name = value

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

127

#define SRI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

128

REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

129

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

131

#define SRI_ARR(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

132

REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

133

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

135

#define SR_ARR_I2C(reg_name, id) \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

136

REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

138

#define SRI_ARR_I2C(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

139

REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

140

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

142

#define SRI_ARR_ALPHABET(reg_name, block, index, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

143

REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

144

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

146

#define SRI2(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

147

.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

148

reg ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

149

#define SRI2_ARR(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

150

REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

151

reg ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

153

#define SRIR(var_name, reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

154

.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

155

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

157

#define SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

158

REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

159

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

161

#define SRII_ARR_2(reg_name, block, id, inst)\

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

162

REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

163

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

165

#define SRII_MPC_RMU(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

166

.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

167

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

169

#define SRII_DWB(reg_name, temp_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

170

REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

173

#define SF_DWB2(reg_name, block, id, field_name, post_fix) \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

174

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

176

#define DCCG_SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

177

REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

178

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

180

#define VUPDATE_SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

181

REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

182

reg ## reg_name ## _ ## block ## id

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

190

#define NBIO_SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

191

REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

192

regBIF_BX0_ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

193

#define NBIO_SR_ARR(reg_name, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

194

REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

195

regBIF_BX0_ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

199

#define REG(reg_name) \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

200

(ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

118

#define SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

119

REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

120

reg ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

121

#define SR_ARR(reg_name, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

122

REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

123

reg ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

124

#define SR_ARR_INIT(reg_name, id, value)\

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

125

REG_STRUCT[id].reg_name = value

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

127

#define SRI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

128

REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

129

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

131

#define SRI_ARR(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

132

REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

133

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

135

#define SR_ARR_I2C(reg_name, id) \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

136

REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

138

#define SRI_ARR_I2C(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

139

REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

140

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

142

#define SRI_ARR_ALPHABET(reg_name, block, index, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

143

REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

144

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

146

#define SRI2(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

147

.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

148

reg ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

149

#define SRI2_ARR(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

150

REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

151

reg ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

153

#define SRIR(var_name, reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

154

.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

155

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

157

#define SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

158

REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

159

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

161

#define SRII_ARR_2(reg_name, block, id, inst)\

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

162

REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

163

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

165

#define SRII_MPC_RMU(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

166

.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

167

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

169

#define SRII_DWB(reg_name, temp_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

170

REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

173

#define DCCG_SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

174

REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

175

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

177

#define SF_DWB2(reg_name, block, id, field_name, post_fix) \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

178

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

180

#define VUPDATE_SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

181

REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

182

reg ## reg_name ## _ ## block ## id

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

190

#define NBIO_SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

191

REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

192

regBIF_BX0_ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

193

#define NBIO_SR_ARR(reg_name, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

194

REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

195

regBIF_BX0_ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

198

#define REG(reg_name) \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

199

(ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

132

#define SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

133

REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

134

reg ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

136

#define SR_ARR(reg_name, id) \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

137

REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

139

#define SR_ARR_INIT(reg_name, id, value) \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

140

REG_STRUCT[id].reg_name = value

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

142

#define SRI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

143

REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

144

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

146

#define SRI_ARR(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

147

REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

148

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

150

#define SR_ARR_I2C(reg_name, id) \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

151

REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

153

#define SRI_ARR_I2C(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

154

REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

155

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

157

#define SRI_ARR_ALPHABET(reg_name, block, index, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

158

REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

159

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

161

#define SRI2(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

162

.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

163

reg ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

165

#define SRI2_ARR(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

166

REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

167

reg ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

169

#define SRIR(var_name, reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

170

.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

171

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

173

#define SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

174

REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

175

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

177

#define SRII_ARR_2(reg_name, block, id, inst)\

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

178

REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

179

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

181

#define SRII_MPC_RMU(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

182

.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

183

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

185

#define SRII_DWB(reg_name, temp_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

186

REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

189

#define SF_DWB2(reg_name, block, id, field_name, post_fix) \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

190

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

192

#define DCCG_SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

193

REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

194

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

196

#define VUPDATE_SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

197

REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

198

reg ## reg_name ## _ ## block ## id

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

206

#define NBIO_SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

207

REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

208

regBIF_BX1_ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

210

#define NBIO_SR_ARR(reg_name, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

211

REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

212

regBIF_BX1_ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

112

#define SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

113

REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

114

reg ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

116

#define SR_ARR(reg_name, id) \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

117

REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

119

#define SR_ARR_INIT(reg_name, id, value) \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

120

REG_STRUCT[id].reg_name = value

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

122

#define SRI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

123

REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

124

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

126

#define SRI_ARR(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

127

REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

128

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

130

#define SR_ARR_I2C(reg_name, id) \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

131

REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

133

#define SRI_ARR_I2C(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

134

REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

135

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

137

#define SRI_ARR_ALPHABET(reg_name, block, index, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

138

REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

139

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

141

#define SRI2(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

142

.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

143

reg ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

145

#define SRI2_ARR(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

146

REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

147

reg ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

149

#define SRIR(var_name, reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

150

.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

151

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

153

#define SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

154

REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

155

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

157

#define SRII_ARR_2(reg_name, block, id, inst)\

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

158

REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

159

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

161

#define SRII_MPC_RMU(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

162

.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

163

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

165

#define SRII_DWB(reg_name, temp_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

166

REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

169

#define SF_DWB2(reg_name, block, id, field_name, post_fix) \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

170

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

172

#define DCCG_SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

173

REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

174

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

176

#define VUPDATE_SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

177

REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

178

reg ## reg_name ## _ ## block ## id

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

186

#define NBIO_SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

187

REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

188

regBIF_BX1_ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

190

#define NBIO_SR_ARR(reg_name, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

191

REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

192

regBIF_BX1_ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

117

#define SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

118

REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

119

reg ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

121

#define SR_ARR(reg_name, id) \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

122

REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

124

#define SR_ARR_INIT(reg_name, id, value) \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

125

REG_STRUCT[id].reg_name = value

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

127

#define SRI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

128

REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

129

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

131

#define SRI_ARR(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

132

REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

133

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

135

#define SR_ARR_I2C(reg_name, id) \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

136

REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

138

#define SRI_ARR_I2C(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

139

REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

140

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

142

#define SRI_ARR_ALPHABET(reg_name, block, index, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

143

REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

144

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

146

#define SRI2(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

147

.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

148

reg ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

150

#define SRI2_ARR(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

151

REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

152

reg ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

154

#define SRIR(var_name, reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

155

.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

156

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

158

#define SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

159

REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

160

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

162

#define SRII_ARR_2(reg_name, block, id, inst)\

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

163

REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

164

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

166

#define SRII_MPC_RMU(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

167

.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

168

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

170

#define SRII_DWB(reg_name, temp_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

171

REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

174

#define SF_DWB2(reg_name, block, id, field_name, post_fix) \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

175

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

177

#define DCCG_SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

178

REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

179

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

181

#define VUPDATE_SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

182

REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

183

reg ## reg_name ## _ ## block ## id

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

191

#define NBIO_SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

192

REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

193

regBIF_BX2_ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

195

#define NBIO_SR_ARR(reg_name, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

196

REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

197

regBIF_BX2_ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

100

REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

101

reg ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

102

#define SR_ARR(reg_name, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

103

REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

104

reg ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

105

#define SR_ARR_INIT(reg_name, id, value)\

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

106

REG_STRUCT[id].reg_name = value

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

108

#define SRI(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

109

REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

110

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

112

#define SRI_ARR(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

113

REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

114

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

119

#define SRI_ARR_US(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

120

REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

121

reg ## block ## id ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

122

#define SR_ARR_I2C(reg_name, id) \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

123

REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

125

#define SRI_ARR_I2C(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

126

REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

127

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

129

#define SRI_ARR_ALPHABET(reg_name, block, index, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

130

REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

131

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

133

#define SRI2(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

134

.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

135

reg ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

136

#define SRI2_ARR(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

137

REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

138

reg ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

140

#define SRIR(var_name, reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

141

.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

142

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

144

#define SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

145

REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

146

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

148

#define SRII_ARR_2(reg_name, block, id, inst)\

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

149

REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

150

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

152

#define SRII_MPC_RMU(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

153

.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

154

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

156

#define SRII_DWB(reg_name, temp_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

157

REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

160

#define DCCG_SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

161

REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

162

reg ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

164

#define SF_DWB2(reg_name, block, id, field_name, post_fix) \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

165

.field_name = reg_name ## __ ## field_name ## post_fix

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

167

#define VUPDATE_SRII(reg_name, block, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

168

REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

169

reg ## reg_name ## _ ## block ## id

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

177

#define NBIO_SR(reg_name)\

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

178

REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

179

regBIF_BX0_ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

180

#define NBIO_SR_ARR(reg_name, id)\

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

181

REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

182

regBIF_BX0_ ## reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

185

#define REG(reg_name) \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

186

(ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

99

#define SR(reg_name)\

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

37

#define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn314.c

43

#define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn315.c

43

#define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn316.c

43

#define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

38

#define REG_OFFSET_EXP(reg_name) BASE(reg##reg_name##_BASE_IDX) + reg##reg_name

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

38

#define REG_OFFSET_EXP(reg_name) BASE(reg##reg_name##_BASE_IDX) + reg##reg_name

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn351.c

14

#define REG_OFFSET_EXP(reg_name) BASE(reg##reg_name##_BASE_IDX) + reg##reg_name

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn36.c

14

#define REG_OFFSET_EXP(reg_name) BASE(reg##reg_name##_BASE_IDX) + reg##reg_name

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

17

#define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h

111

#define REG_GET(reg_name, field, val) \

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h

112

dmub_reg_get(CTX, REG(reg_name), FN(reg_name, field), val)

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h

37

#define REG_OFFSET(reg_name) (BASE(mm##reg_name##_BASE_IDX) + mm##reg_name)

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h

39

#define FD_SHIFT(reg_name, field) reg_name##__##field##__SHIFT

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h

41

#define FD_MASK(reg_name, field) reg_name##__##field##_MASK

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h

47

#define FN(reg_name, field) FD(reg_name##__##field)

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h

58

#define REG_SET_N(reg_name, n, initial_val, ...) \

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h

59

dmub_reg_set(CTX, REG(reg_name), initial_val, n, __VA_ARGS__)

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h

61

#define REG_SET(reg_name, initial_val, field, val) \

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h

62

REG_SET_N(reg_name, 1, initial_val, \

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h

63

FN(reg_name, field), val)

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h

85

#define REG_UPDATE_N(reg_name, n, ...)\

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h

86

dmub_reg_update(CTX, REG(reg_name), n, __VA_ARGS__)

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h

88

#define REG_UPDATE(reg_name, field, val) \

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h

89

REG_UPDATE_N(reg_name, 1, \

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h

90

FN(reg_name, field), val)

drivers/gpu/drm/i915/gvt/trace.h

276

TP_PROTO(int id, char *reg_name, unsigned int reg, unsigned int new_val,

drivers/gpu/drm/i915/gvt/trace.h

279

TP_ARGS(id, reg_name, reg, new_val, old_val, changed),

drivers/gpu/drm/i915/gvt/trace.h

292

snprintf(__entry->buf, GVT_TEMP_STR_LEN, "%s", reg_name);

drivers/gpu/drm/omapdrm/dss/video-pll.c

136

const char * const reg_name[] = { "pll1", "pll2" };

drivers/gpu/drm/omapdrm/dss/video-pll.c

148

pll_base = devm_platform_ioremap_resource_byname(pdev, reg_name[id]);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

204

const char *reg_name)

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

209

DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name);

drivers/hv/mshv_vtl_main.c

510

enum hv_register_name reg_name;

drivers/hv/mshv_vtl_main.c

579

if (reg_table[i].reg_name != gpr_name)

drivers/hwmon/mr75203.c

581

static int pvt_get_regmap(struct platform_device *pdev, char *reg_name,

drivers/hwmon/mr75203.c

588

if (!strcmp(reg_name, "common"))

drivers/hwmon/mr75203.c

590

else if (!strcmp(reg_name, "ts"))

drivers/hwmon/mr75203.c

592

else if (!strcmp(reg_name, "pd"))

drivers/hwmon/mr75203.c

594

else if (!strcmp(reg_name, "vm"))

drivers/hwmon/mr75203.c

599

io_base = devm_platform_ioremap_resource_byname(pdev, reg_name);

drivers/hwmon/mr75203.c

603

pvt_regmap_config.name = reg_name;

drivers/iio/adc/fsl-imx25-gcq.c

178

char reg_name[12];

drivers/iio/adc/fsl-imx25-gcq.c

184

ret = snprintf(reg_name, sizeof(reg_name), "vref-%s",

drivers/iio/adc/fsl-imx25-gcq.c

189

priv->vref[refp] = devm_regulator_get_optional(dev, reg_name);

drivers/iio/adc/fsl-imx25-gcq.c

193

reg_name);

drivers/leds/leds-bd2802.c

318

#define BD2802_SET_REGISTER(reg_addr, reg_name) \

drivers/leds/leds-bd2802.c

336

.attr = {.name = reg_name, .mode = 0644}, \

drivers/media/dvb-frontends/au8522_decoder.c

284

au8522_writereg(state, filter_coef[i].reg_name,

drivers/media/dvb-frontends/au8522_decoder.c

40

u16 reg_name;

drivers/media/dvb-frontends/au8522_decoder.c

406

au8522_writereg(state, lpfilter_coef[i].reg_name,

drivers/media/i2c/ccs/ccs-reg-access.h

33

#define ccs_read(sensor, reg_name, val) \

drivers/media/i2c/ccs/ccs-reg-access.h

34

ccs_read_addr(sensor, CCS_R_##reg_name, val)

drivers/media/i2c/ccs/ccs-reg-access.h

36

#define ccs_write(sensor, reg_name, val) \

drivers/media/i2c/ccs/ccs-reg-access.h

37

ccs_write_addr(sensor, CCS_R_##reg_name, val)

drivers/media/platform/nxp/imx-jpeg/mxc-jpeg-hw.c

15

#define internal_print_wrapper_reg(dev, base_address, reg_name, reg_offset) {\

drivers/media/platform/nxp/imx-jpeg/mxc-jpeg-hw.c

18

dev_dbg(dev, "Wrapper reg %s = 0x%x\n", reg_name, val);\

drivers/media/platform/verisilicon/hantro_postproc.c

17

#define HANTRO_PP_REG_WRITE(vpu, reg_name, val) \

drivers/media/platform/verisilicon/hantro_postproc.c

20

&hantro_g1_postproc_regs.reg_name, \

drivers/media/platform/verisilicon/hantro_postproc.c

24

#define HANTRO_PP_REG_WRITE_RELAXED(vpu, reg_name, val) \

drivers/media/platform/verisilicon/hantro_postproc.c

27

&hantro_g1_postproc_regs.reg_name, \

drivers/mtd/nand/raw/tegra_nand.c

318

const char *reg_name = tegra_nand_reg_names[i];

drivers/mtd/nand/raw/tegra_nand.c

320

if (!reg_name)

drivers/mtd/nand/raw/tegra_nand.c

324

dev_err(ctrl->dev, "%s: 0x%08x\n", reg_name, reg);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1203

.reg_name = "SSU_BP_STATUS_0~5",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1207

.reg_name = "LO_PRI_UNICAST_CUR_CNT",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1211

.reg_name = "HI/LO_PRI_MULTICAST_CUR_CNT",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1215

.reg_name = "SSU_MB_RD_RLT_DROP_CNT",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1219

.reg_name = "SSU_PPP_MAC_KEY_NUM",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1223

.reg_name = "SSU_PPP_HOST_KEY_NUM",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1227

.reg_name = "PPP_SSU_MAC/HOST_RLT_NUM",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1231

.reg_name = "FULL/PART_DROP_NUM",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1235

.reg_name = "PPP_KEY/RLT_DROP_NUM",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1239

.reg_name = "NIC/ROC_L2_ERR_DROP_PKT_CNT",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1243

.reg_name = "NIC/ROC_L2_ERR_DROP_PKT_CNT_RX",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1251

.reg_name = "RX_PACKET_IN/OUT_CNT",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1255

.reg_name = "TX_PACKET_IN/OUT_CNT",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1259

.reg_name = "RX_PACKET_TC0_IN/OUT_CNT",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1263

.reg_name = "RX_PACKET_TC1_IN/OUT_CNT",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1267

.reg_name = "RX_PACKET_TC2_IN/OUT_CNT",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1271

.reg_name = "RX_PACKET_TC3_IN/OUT_CNT",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1275

.reg_name = "RX_PACKET_TC4_IN/OUT_CNT",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1279

.reg_name = "RX_PACKET_TC5_IN/OUT_CNT",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1283

.reg_name = "RX_PACKET_TC6_IN/OUT_CNT",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1287

.reg_name = "RX_PACKET_TC7_IN/OUT_CNT",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1291

.reg_name = "TX_PACKET_TC0_IN/OUT_CNT",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1295

.reg_name = "TX_PACKET_TC1_IN/OUT_CNT",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1299

.reg_name = "TX_PACKET_TC2_IN/OUT_CNT",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1303

.reg_name = "TX_PACKET_TC3_IN/OUT_CNT",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1307

.reg_name = "TX_PACKET_TC4_IN/OUT_CNT",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1311

.reg_name = "TX_PACKET_TC5_IN/OUT_CNT",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1315

.reg_name = "TX_PACKET_TC6_IN/OUT_CNT",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1319

.reg_name = "TX_PACKET_TC7_IN/OUT_CNT",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1323

.reg_name = "PACKET_TC0~3_CURR_BUFFER_CNT",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1327

.reg_name = "PACKET_TC4~7_CURR_BUFFER_CNT",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1331

.reg_name = "ROC_RX_PACKET_IN_CNT",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1335

.reg_name = "ROC_TX_PACKET_OUT_CNT",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1343

.reg_name = "RPU_FSM_DFX_ST0/ST1_TNL",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1348

.reg_name = "RPU_RX_PKT_DROP_CNT_TNL",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1357

.reg_name = "FIFO_DFX_ST0_1_2_4",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1365

.reg_name = "IGU_RX_ERR_PKT",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1369

.reg_name = "IGU_RX_OUT_ALL_PKT",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1373

.reg_name = "EGU_TX_OUT_ALL_PKT",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1377

.reg_name = "EGU_TX_ERR_PKT",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1385

.reg_name = "SSU2RPU_TNL_WR_PKT_CNT_TNL",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1390

.reg_name = "RPU2HST_TNL_WR_PKT_CNT_TNL",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1399

.reg_name = "SSU_OVERSIZE_DROP_CNT",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1403

.reg_name = "ROCE_RX_BYPASS_5NS_DROP_NUM",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1407

.reg_name = "RX_PKT_IN/OUT_ERR_CNT",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1411

.reg_name = "TX_PKT_IN/OUT_ERR_CNT",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1415

.reg_name = "ETS_TC_READY",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1419

.reg_name = "MIB_TX/RX_BAD_PKTS",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1423

.reg_name = "MIB_TX/RX_GOOD_PKTS",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1427

.reg_name = "MIB_TX/RX_TOTAL_PKTS",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1431

.reg_name = "MIB_TX/RX_PAUSE_PKTS",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1435

.reg_name = "MIB_TX_ERR_ALL_PKTS",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1439

.reg_name = "MIB_RX_FCS_ERR_PKTS",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1443

.reg_name = "IGU_EGU_AUTO_GATE_EN",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1447

.reg_name = "IGU_EGU_INT_SRC",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1451

.reg_name = "EGU_READY_NUM_CFG",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1455

.reg_name = "IGU_EGU_TNL_DFX",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1459

.reg_name = "TX_TNL_NOTE_PKT",

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1519

actual_len = strlen(reg_info[i].reg_name) +

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1524

reg_info[i].reg_name, actual_len);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

1529

reg_info[i].reg_name);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h

236

const char *reg_name;

drivers/net/ethernet/intel/e1000/e1000_main.c

3292

static const char * const reg_name[] = {

drivers/net/ethernet/intel/e1000/e1000_main.c

3348

pr_info("%-15s %08x\n", reg_name[i], regs_buff[i]);

drivers/net/ethernet/sun/niu.c

137

const char *reg_name)

drivers/net/ethernet/sun/niu.c

145

(unsigned long long)bits, reg_name,

drivers/net/ethernet/sun/niu.c

172

const char *reg_name)

drivers/net/ethernet/sun/niu.c

184

(unsigned long long)bits, reg_name,

drivers/net/ethernet/sun/niu.c

216

const char *reg_name)

drivers/net/ethernet/sun/niu.c

224

(unsigned long long)bits, reg_name,

drivers/net/pse-pd/pd692x0.c

938

pd692x0_register_manager_regulator(struct device *dev, char *reg_name,

drivers/net/pse-pd/pd692x0.c

955

rdesc->name = reg_name;

drivers/net/pse-pd/pd692x0.c

992

char *reg_name;

drivers/net/pse-pd/pd692x0.c

995

reg_name = devm_kzalloc(dev, reg_name_len, GFP_KERNEL);

drivers/net/pse-pd/pd692x0.c

996

if (!reg_name)

drivers/net/pse-pd/pd692x0.c

998

snprintf(reg_name, 26, "pse-%s-manager%d", dev_name(dev), i);

drivers/net/pse-pd/pd692x0.c

999

rdev = pd692x0_register_manager_regulator(dev, reg_name,

drivers/net/pse-pd/pse_core.c

1081

char *reg_name;

drivers/net/pse-pd/pse_core.c

1087

reg_name = devm_kzalloc(pcdev->dev, reg_name_len, GFP_KERNEL);

drivers/net/pse-pd/pse_core.c

1088

if (!reg_name)

drivers/net/pse-pd/pse_core.c

1091

snprintf(reg_name, reg_name_len, "pse-%s_pi%d",

drivers/net/pse-pd/pse_core.c

1094

ret = devm_pse_pi_regulator_register(pcdev, reg_name, i);

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

25

#define READ_RADIO_REG2(pi, radio_type, jspace, core, reg_name) \

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

26

read_radio_reg(pi, radio_type##_##jspace##_##reg_name | \

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

31

#define WRITE_RADIO_REG2(pi, radio_type, jspace, core, reg_name, value) \

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

32

write_radio_reg(pi, radio_type##_##jspace##_##reg_name | \

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

37

#define WRITE_RADIO_SYN(pi, radio_type, reg_name, value) \

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

38

write_radio_reg(pi, radio_type##_##SYN##_##reg_name, value)

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

40

#define READ_RADIO_REG3(pi, radio_type, jspace, core, reg_name) \

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

42

radio_type##_##jspace##0##_##reg_name : \

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

43

radio_type##_##jspace##1##_##reg_name))

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

45

#define WRITE_RADIO_REG3(pi, radio_type, jspace, core, reg_name, value) \

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

47

radio_type##_##jspace##0##_##reg_name : \

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

48

radio_type##_##jspace##1##_##reg_name), \

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

51

#define READ_RADIO_REG4(pi, radio_type, jspace, core, reg_name) \

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

53

radio_type##_##reg_name##_##jspace##0 : \

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

54

radio_type##_##reg_name##_##jspace##1))

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

56

#define WRITE_RADIO_REG4(pi, radio_type, jspace, core, reg_name, value) \

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

58

radio_type##_##reg_name##_##jspace##0 : \

drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c

59

radio_type##_##reg_name##_##jspace##1), \

drivers/net/wireless/intel/iwlwifi/mld/fw.c

212

#define IWL_FW_PRINT_REG_INFO(reg_name) \

drivers/net/wireless/intel/iwlwifi/mld/fw.c

213

IWL_ERR(mld, #reg_name ": 0x%x\n", iwl_read_umac_prph(trans, reg_name))

drivers/net/wireless/intel/iwlwifi/mvm/fw.c

265

#define IWL_FW_PRINT_REG_INFO(reg_name) \

drivers/net/wireless/intel/iwlwifi/mvm/fw.c

266

IWL_ERR(mvm, #reg_name ": 0x%x\n", iwl_read_umac_prph(trans, reg_name))

drivers/opp/ti-opp-supply.c

223

char *reg_name)

drivers/opp/ti-opp-supply.c

255

dev_dbg(dev, "%s scaling to %luuV[min %luuV max %luuV]\n", reg_name,

drivers/opp/ti-opp-supply.c

265

reg_name, vdd_uv, supply->u_volt_min,

drivers/pci/controller/dwc/pcie-designware.c

1291

const char *reg_name,

drivers/pci/controller/dwc/pcie-designware.c

1301

index = of_property_match_string(np, "reg-names", reg_name);

drivers/pci/controller/dwc/pcie-designware.c

1304

dev_err(dev, "No %s in devicetree \"reg\" property\n", reg_name);

drivers/pci/controller/dwc/pcie-designware.c

1315

reg_name, index, reg_addr, fixup_addr,

drivers/pci/controller/dwc/pcie-designware.c

1319

reg_name, index, reg_addr, fixup_addr,

drivers/pci/controller/dwc/pcie-designware.c

1336

reg_name, index, reg_addr,

drivers/pci/controller/dwc/pcie-designware.c

1341

reg_name, index, reg_addr,

drivers/pci/controller/dwc/pcie-designware.h

610

const char *reg_name,

drivers/regulator/event.c

30

int reg_generate_netlink_event(const char *reg_name, u64 event)

drivers/regulator/event.c

64

strscpy(edata->reg_name, reg_name, sizeof(edata->reg_name));

drivers/regulator/regnl.h

11

int reg_generate_netlink_event(const char *reg_name, u64 event);

drivers/video/fbdev/omap2/omapfb/dss/video-pll.c

128

const char * const reg_name[] = { "pll1", "pll2" };

drivers/video/fbdev/omap2/omapfb/dss/video-pll.c

140

pll_base = devm_platform_ioremap_resource_byname(pdev, reg_name[id]);

drivers/watchdog/octeon-wdt-main.c

188

static const char reg_name[][3] = {

drivers/watchdog/octeon-wdt-main.c

232

octeon_wdt_write_string(reg_name[i]);

include/uapi/regulator/regulator.h

60

char reg_name[32];

kernel/bpf/btf.c

9575

const char *reg_name, *arg_name, *search_needle;

kernel/bpf/btf.c

9588

reg_name = btf_name_by_offset(reg_btf, reg_type->name_off);

kernel/bpf/btf.c

9591

reg_len = strlen(reg_name);

kernel/bpf/btf.c

9612

search_needle = strstr(reg_name, NOCAST_ALIAS_SUFFIX);

kernel/bpf/btf.c

9623

return !strncmp(reg_name, arg_name, cmp_len);

kernel/bpf/verifier.c

14108

static int check_return_code(struct bpf_verifier_env *env, int regno, const char *reg_name);

kernel/bpf/verifier.c

17936

static int check_return_code(struct bpf_verifier_env *env, int regno, const char *reg_name)

kernel/bpf/verifier.c

18121

verbose_invalid_scalar(env, reg, range, exit_ctx, reg_name);

kernel/bpf/verifier.c

388

const char *reg_name)

kernel/bpf/verifier.c

392

verbose(env, "%s the register %s has", ctx, reg_name);

kernel/bpf/verifier.c

5989

const char *reg_name = "";

kernel/bpf/verifier.c

6007

reg_name = btf_type_name(reg->btf, reg->btf_id);

kernel/bpf/verifier.c

6049

reg_type_str(env, reg->type), reg_name);

kernel/trace/trace_events_user.c

1963

user->reg_name, user->group->multi_id);

kernel/trace/trace_events_user.c

1975

user->call.name = user->reg_name;

kernel/trace/trace_events_user.c

1976

user->tracepoint.name = user->reg_name;

kernel/trace/trace_events_user.c

2118

user->reg_name = name;

kernel/trace/trace_events_user.c

37

#define EVENT_NAME(user_event) ((user_event)->reg_name)

kernel/trace/trace_events_user.c

85

char *reg_name;

sound/soc/renesas/rcar/gen.c

210

gen->reg_name[conf[i].idx] = conf[i].reg_name;

sound/soc/renesas/rcar/gen.c

30

const char *reg_name[REG_MAX];

sound/soc/renesas/rcar/gen.c

34

#define rsnd_reg_name(gen, id) ((gen)->reg_name[id])

sound/soc/renesas/rcar/gen.c

40

const char *reg_name;

sound/soc/renesas/rcar/gen.c

48

.reg_name = n, \

tools/arch/x86/kcpuid/kcpuid.c

498

static void show_reg_header(bool has_entries, u32 leaf, u32 subleaf, const char *reg_name)

tools/arch/x86/kcpuid/kcpuid.c

501

printf("CPUID_0x%x_%s[0x%x]:\n", leaf, reg_name, subleaf);

tools/lib/bpf/usdt.c

1247

static int calc_pt_regs_off(const char *reg_name)

tools/lib/bpf/usdt.c

1283

if (strcmp(reg_name, reg_map[i].names[j]) == 0)

tools/lib/bpf/usdt.c

1288

pr_warn("usdt: unrecognized register '%s'\n", reg_name);

tools/lib/bpf/usdt.c

1294

char reg_name[16] = {0}, idx_reg_name[16] = {0};

tools/lib/bpf/usdt.c

1299

arg_sz, &off, reg_name, idx_reg_name, &scale, &len) == 5 ||

tools/lib/bpf/usdt.c

1301

arg_sz, reg_name, idx_reg_name, &scale, &len) == 4 ||

tools/lib/bpf/usdt.c

1303

arg_sz, &off, reg_name, idx_reg_name, &len) == 4 ||

tools/lib/bpf/usdt.c

1305

arg_sz, reg_name, idx_reg_name, &len) == 3

tools/lib/bpf/usdt.c

1317

reg_off = calc_pt_regs_off(reg_name);

tools/lib/bpf/usdt.c

1338

arg_sz, &off, reg_name, &len) == 3) {

tools/lib/bpf/usdt.c

1342

reg_off = calc_pt_regs_off(reg_name);

tools/lib/bpf/usdt.c

1346

} else if (sscanf(arg_str, " %d @ ( %%%15[^)] ) %n", arg_sz, reg_name, &len) == 2) {

tools/lib/bpf/usdt.c

1350

reg_off = calc_pt_regs_off(reg_name);

tools/lib/bpf/usdt.c

1354

} else if (sscanf(arg_str, " %d @ %%%15s %n", arg_sz, reg_name, &len) == 2) {

tools/lib/bpf/usdt.c

1360

reg_off = calc_pt_regs_off(reg_name);

tools/lib/bpf/usdt.c

1418

static int calc_pt_regs_off(const char *reg_name)

tools/lib/bpf/usdt.c

1422

if (sscanf(reg_name, "x%d", &reg_num) == 1) {

tools/lib/bpf/usdt.c

1425

} else if (strcmp(reg_name, "sp") == 0) {

tools/lib/bpf/usdt.c

1428

pr_warn("usdt: unrecognized register '%s'\n", reg_name);

tools/lib/bpf/usdt.c

1434

char reg_name[16];

tools/lib/bpf/usdt.c

1438

if (sscanf(arg_str, " %d @ \[ %15[a-z0-9] , %ld ] %n", arg_sz, reg_name, &off, &len) == 3) {

tools/lib/bpf/usdt.c

1442

reg_off = calc_pt_regs_off(reg_name);

tools/lib/bpf/usdt.c

1446

} else if (sscanf(arg_str, " %d @ \[ %15[a-z0-9] ] %n", arg_sz, reg_name, &len) == 2) {

tools/lib/bpf/usdt.c

1450

reg_off = calc_pt_regs_off(reg_name);

tools/lib/bpf/usdt.c

1459

} else if (sscanf(arg_str, " %d @ %15[a-z0-9] %n", arg_sz, reg_name, &len) == 2) {

tools/lib/bpf/usdt.c

1463

reg_off = calc_pt_regs_off(reg_name);

tools/lib/bpf/usdt.c

1477

static int calc_pt_regs_off(const char *reg_name)

tools/lib/bpf/usdt.c

1518

if (strcmp(reg_name, reg_map[i].name) == 0)

tools/lib/bpf/usdt.c

1522

pr_warn("usdt: unrecognized register '%s'\n", reg_name);

tools/lib/bpf/usdt.c

1528

char reg_name[16];

tools/lib/bpf/usdt.c

1532

if (sscanf(arg_str, " %d @ %ld ( %15[a-z0-9] ) %n", arg_sz, &off, reg_name, &len) == 3) {

tools/lib/bpf/usdt.c

1536

reg_off = calc_pt_regs_off(reg_name);

tools/lib/bpf/usdt.c

1545

} else if (sscanf(arg_str, " %d @ %15[a-z0-9] %n", arg_sz, reg_name, &len) == 2) {

tools/lib/bpf/usdt.c

1549

reg_off = calc_pt_regs_off(reg_name);

tools/lib/bpf/usdt.c

1563

static int calc_pt_regs_off(const char *reg_name)

tools/lib/bpf/usdt.c

1589

if (strcmp(reg_name, reg_map[i].name) == 0)

tools/lib/bpf/usdt.c

1593

pr_warn("usdt: unrecognized register '%s'\n", reg_name);

tools/lib/bpf/usdt.c

1599

char reg_name[16];

tools/lib/bpf/usdt.c

1604

arg_sz, reg_name, &off, &len) == 3) {

tools/lib/bpf/usdt.c

1608

reg_off = calc_pt_regs_off(reg_name);

tools/lib/bpf/usdt.c

1612

} else if (sscanf(arg_str, " %d @ \[ %15[a-z0-9] ] %n", arg_sz, reg_name, &len) == 2) {

tools/lib/bpf/usdt.c

1616

reg_off = calc_pt_regs_off(reg_name);

tools/lib/bpf/usdt.c

1625

} else if (sscanf(arg_str, " %d @ %15[a-z0-9] %n", arg_sz, reg_name, &len) == 2) {

tools/lib/bpf/usdt.c

1629

reg_off = calc_pt_regs_off(reg_name);

tools/objtool/arch/loongarch/orc.c

152

printf("%s + %3d", reg_name(reg), offset);

tools/objtool/arch/x86/orc.c

173

printf("%s%+d", reg_name(reg), offset);

tools/perf/util/perf_regs.c

123

const char *reg_name = NULL;

tools/perf/util/perf_regs.c

127

reg_name = __perf_reg_name_arm(id);

tools/perf/util/perf_regs.c

130

reg_name = __perf_reg_name_arm64(id);

tools/perf/util/perf_regs.c

133

reg_name = __perf_reg_name_csky(id, e_flags);

tools/perf/util/perf_regs.c

136

reg_name = __perf_reg_name_loongarch(id);

tools/perf/util/perf_regs.c

139

reg_name = __perf_reg_name_mips(id);

tools/perf/util/perf_regs.c

143

reg_name = __perf_reg_name_powerpc(id);

tools/perf/util/perf_regs.c

146

reg_name = __perf_reg_name_riscv(id);

tools/perf/util/perf_regs.c

149

reg_name = __perf_reg_name_s390(id);

tools/perf/util/perf_regs.c

153

reg_name = __perf_reg_name_x86(id);

tools/perf/util/perf_regs.c

158

if (reg_name)

tools/perf/util/perf_regs.c

159

return reg_name;

tools/testing/selftests/kvm/arm64/debug-exceptions.c

40

#define GEN_DEBUG_WRITE_REG(reg_name) \

tools/testing/selftests/kvm/arm64/debug-exceptions.c

41

static void write_##reg_name(int num, uint64_t val) \

tools/testing/selftests/kvm/arm64/debug-exceptions.c

45

write_sysreg(val, reg_name##0_el1); \

tools/testing/selftests/kvm/arm64/debug-exceptions.c

48

write_sysreg(val, reg_name##1_el1); \

tools/testing/selftests/kvm/arm64/debug-exceptions.c

51

write_sysreg(val, reg_name##2_el1); \

tools/testing/selftests/kvm/arm64/debug-exceptions.c

54

write_sysreg(val, reg_name##3_el1); \

tools/testing/selftests/kvm/arm64/debug-exceptions.c

57

write_sysreg(val, reg_name##4_el1); \

tools/testing/selftests/kvm/arm64/debug-exceptions.c

60

write_sysreg(val, reg_name##5_el1); \

tools/testing/selftests/kvm/arm64/debug-exceptions.c

63

write_sysreg(val, reg_name##6_el1); \

tools/testing/selftests/kvm/arm64/debug-exceptions.c

66

write_sysreg(val, reg_name##7_el1); \

tools/testing/selftests/kvm/arm64/debug-exceptions.c

69

write_sysreg(val, reg_name##8_el1); \

tools/testing/selftests/kvm/arm64/debug-exceptions.c

72

write_sysreg(val, reg_name##9_el1); \

tools/testing/selftests/kvm/arm64/debug-exceptions.c

75

write_sysreg(val, reg_name##10_el1); \

tools/testing/selftests/kvm/arm64/debug-exceptions.c

78

write_sysreg(val, reg_name##11_el1); \

tools/testing/selftests/kvm/arm64/debug-exceptions.c

81

write_sysreg(val, reg_name##12_el1); \

tools/testing/selftests/kvm/arm64/debug-exceptions.c

84

write_sysreg(val, reg_name##13_el1); \

tools/testing/selftests/kvm/arm64/debug-exceptions.c

87

write_sysreg(val, reg_name##14_el1); \

tools/testing/selftests/kvm/arm64/debug-exceptions.c

90

write_sysreg(val, reg_name##15_el1); \