reg_high
_EMIT4((op) | reg_high(b3) << 8 | reg(b1, b2)); \
_EMIT4_DISP((op) | reg_high(b1) << 16 | \
reg_high(b2) << 8, (disp)); \
_EMIT4((op) | reg_high(b1) << 16 | __imm); \
reg_high(b3) << 8, op2, disp); \
_EMIT6((op1) | (reg_high(b1) | (mask)) << 16 | \
emit6_pcrel_ril(jit, op | reg_high(b) << 16, pcrel);
_EMIT6_IMM((op) | reg_high(b1) << 16, imm); \
u32 reg_lvl, reg_val, reg_val_lvl, mask, reg_high, reg_shift;
reg_high = ((xin_id & 0x8) >> 3) * 4 + (level * 8);
reg_val = DPU_REG_READ(c, VBIF_XINL_QOS_RP_REMAP_000 + reg_high);
reg_val_lvl = DPU_REG_READ(c, reg_lvl + reg_high);
DPU_REG_WRITE(c, VBIF_XINL_QOS_RP_REMAP_000 + reg_high, reg_val);
DPU_REG_WRITE(c, reg_lvl + reg_high, reg_val_lvl);
reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */
csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
if (ixgbe_out_i2c_byte_ack(hw, reg_high))
u8 reg_high;
reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */
csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
if (ixgbe_out_i2c_byte_ack(hw, reg_high))
u8 reg_high;