reg_enable
int i, max_slots, ctrl_reg, val_reg, reg_enable;
reg_enable = !debug_info->bps_disabled;
reg_enable = !debug_info->wps_disabled;
reg_enable ? ctrl | 0x1 : ctrl & ~0x1);
u32 reg_enable;
.reg_enable = 0x0,
.reg_enable = 0x0,
if (!(readl_relaxed(data->base + qcom_cpufreq.soc_data->reg_enable) & 0x1)) {
intc.enable[b] = base + reg_enable[b];
static const int reg_enable[] __initconst = { 0x18, 0x10, 0x14 };
pending &= __raw_readl(cpu->map_base + reg_enable(intc, idx));
intc->cpus[cpu_idx]->map_base + reg_enable(intc, word));
intc->cpus[cpu_idx]->map_base + reg_enable(intc, word));
__raw_writel(0, cpu->map_base + reg_enable(intc, i));
ASSERT_EQ(0, reg_enable(&self->check, sizeof(int), 0));
ASSERT_EQ(0, reg_enable(&self->check, sizeof(int), 0));
ASSERT_EQ(0, reg_enable(&self->check, sizeof(int), 31));
ASSERT_NE(0, reg_enable(&self->check, sizeof(int), 32));
ASSERT_EQ(0, reg_enable(&self->check_long, sizeof(long), 63));
ASSERT_NE(0, reg_enable(&self->check_long, sizeof(long), 64));
ASSERT_NE(0, reg_enable(&self->check, 1, 0));
ASSERT_NE(0, reg_enable(&self->check, 2, 0));
ASSERT_NE(0, reg_enable(&self->check, 3, 0));
ASSERT_NE(0, reg_enable(&self->check, 5, 0));
ASSERT_NE(0, reg_enable(&self->check, 6, 0));
ASSERT_NE(0, reg_enable(&self->check, 7, 0));
ASSERT_NE(0, reg_enable(&self->check, 9, 0));
ASSERT_NE(0, reg_enable(&self->check, 128, 0));
ASSERT_EQ(0, reg_enable(&self->check, sizeof(int), 0));
ASSERT_EQ(0, reg_enable(&self->check, sizeof(int), 0));