reg_desc
char reg_desc[32];
snprintf(reg_desc, ARRAY_SIZE(reg_desc), "LowerCP");
snprintf(reg_desc, ARRAY_SIZE(reg_desc), "stream%u", i);
qm_name, reg_desc,
char reg_desc[32];
snprintf(reg_desc, ARRAY_SIZE(reg_desc), "LowerQM");
snprintf(reg_desc, ARRAY_SIZE(reg_desc), "stream%u", i);
"%s. err cause: %s", reg_desc,
struct dispc_reg_field reg_desc[DISPC_MGR_FLD_NUM];
.reg_desc = {
.reg_desc = {
.reg_desc = {
.reg_desc = {
const struct dispc_reg_field *rfld = &mgr_desc[channel].reg_desc[regfld];
const struct dispc_reg_field *rfld = &mgr_desc[channel].reg_desc[regfld];
const struct __guc_mmio_reg_descr *reg_desc = &list->list[i];
reg = guc_capture_find_reg(reginfo, reg_desc->reg.addr, reg_desc->flags);
switch (reg_desc->data_type) {
drm_printf(p, "\t%s: 0x%016llx\n", reg_desc->regname, value_qw);
if (FIELD_GET(GUC_REGSET_STEERING_NEEDED, reg_desc->flags))
drm_printf(p, "\t%s[%u]: 0x%08x\n", reg_desc->regname,
reg_desc->dss_id, value);
drm_printf(p, "\t%s: 0x%08x\n", reg_desc->regname, value);
.reg_desc = adp1050_reg_desc,
.reg_desc = ir38064_reg_desc,
info->reg_desc = lm25066_reg_desc;
.reg_desc = lt3074_reg_desc,
info->reg_desc = ltc2978_reg_desc;
info->reg_desc = ltc2978_reg_desc_default;
.reg_desc = mp2975_reg_desc,
.reg_desc = mp2975_reg_desc,
info->reg_desc = mpq7932_regulators_desc_one;
info->reg_desc = mpq7932_regulators_desc;
.reg_desc = &pli1209bc_reg_desc,
const struct regulator_desc *reg_desc;
data->rdevs[i] = devm_regulator_register(dev, &info->reg_desc[i],
info->reg_desc[i].name);
.reg_desc = tda38640_reg_desc,
.reg_desc = tps25990_reg_desc,
.reg_desc = xdpe122_reg_desc,
struct cscfg_regval_desc *reg_desc;
reg_desc = &feat_csdev->feat_desc->regs_desc[i];
reg_csdev->reg_desc.type = reg_desc->type;
if (reg_desc->type & CS_CFG_REG_TYPE_VAL_PARAM)
cscfg_init_reg_param(feat_csdev, reg_desc, reg_csdev);
reg_csdev->reg_desc.val64 = reg_desc->val64;
param_csdev->reg_csdev->reg_desc.val64 = val;
param_csdev->reg_csdev->reg_desc.val32 = (u32)val;
param_csdev->reg_csdev->reg_desc.val64 = val;
param_csdev->reg_csdev->reg_desc.val32 = (u32)val;
u32 tmp32 = reg_csdev->reg_desc.val32;
if (reg_csdev->reg_desc.type & CS_CFG_REG_TYPE_VAL_64BIT) {
*((u64 *)reg_csdev->driver_regval) = reg_csdev->reg_desc.val64;
if (reg_csdev->reg_desc.type & CS_CFG_REG_TYPE_VAL_MASK) {
tmp32 &= ~reg_csdev->reg_desc.mask32;
tmp32 |= reg_csdev->reg_desc.val32 & reg_csdev->reg_desc.mask32;
if (!(reg_csdev->reg_desc.type & CS_CFG_REG_TYPE_VAL_SAVE))
if (reg_csdev->reg_desc.type & CS_CFG_REG_TYPE_VAL_64BIT)
reg_csdev->reg_desc.val64 = *(u64 *)(reg_csdev->driver_regval);
reg_csdev->reg_desc.val32 = *(u32 *)(reg_csdev->driver_regval);
struct cscfg_regval_desc *reg_desc,
param_csdev = &feat_csdev->params_csdev[reg_desc->param_idx];
param_csdev->val64 = reg_csdev->reg_desc.type & CS_CFG_REG_TYPE_VAL_64BIT;
reg_csdev->reg_desc.val64 = param_csdev->current_value;
reg_csdev->reg_desc.val32 = (u32)param_csdev->current_value;
struct cscfg_regval_desc reg_desc;
.reg_desc = {\
.reg_desc = {\
if (info->reg_desc.id == id)
if (info->reg_desc.id == id)
®ulator->info->reg_desc,
regulator->info->reg_desc.name);
struct regulator_desc reg_desc;
.reg_desc = {\
.reg_desc = {\
if (info->reg_desc.id == id)
®ulator->info->reg_desc,
regulator->info->reg_desc.name);
struct regulator_desc reg_desc;
struct regulator_desc *reg_desc;
reg_desc = priv->rdesc + i;
rt5190a_fillin_regulator_desc(reg_desc, i);
match->desc = reg_desc;
struct regulator_desc *reg_desc = &priv->desc;
reg_desc->name = "rt5759-buck";
reg_desc->type = REGULATOR_VOLTAGE;
reg_desc->owner = THIS_MODULE;
reg_desc->ops = &rt5759_regulator_ops;
reg_desc->n_voltages = RT5759_NUM_VOLTS;
reg_desc->min_uV = RT5759_MIN_UV;
reg_desc->uV_step = RT5759_STEP_UV;
reg_desc->vsel_reg = RT5759_REG_VSEL;
reg_desc->vsel_mask = RT5759_VSEL_MASK;
reg_desc->enable_reg = RT5759_REG_DCDCCTRL;
reg_desc->enable_mask = RT5759_ENABLE_MASK;
reg_desc->active_discharge_reg = RT5759_REG_DCDCCTRL;
reg_desc->active_discharge_mask = RT5759_DISCHARGE_MASK;
reg_desc->active_discharge_on = RT5759_DISCHARGE_MASK;
reg_desc->ramp_reg = RT5759_REG_FREQ;
reg_desc->ramp_mask = RT5759_TSTEP_MASK;
reg_desc->ramp_delay_table = rt5759_ramp_table;
reg_desc->n_ramp_values = ARRAY_SIZE(rt5759_ramp_table);
reg_desc->enable_time = RT5759_MINSS_TIMEUS;
reg_desc->of_map_mode = rt5759_of_map_mode;
reg_desc->uV_step = RT5759A_STEP_UV;
reg_cfg.init_data = of_get_regulator_init_data(priv->dev, np, reg_desc);
rdev = devm_regulator_register(priv->dev, reg_desc, ®_cfg);
i < be32_to_cpu(prdf->reg_d1.reg_desc.count); i++)
prdf->reg_d1.reg_desc.desc_tag = cpu_to_be32(ELS_DTAG_FPIN_REGISTER);
prdf->reg_d1.reg_desc.desc_len = cpu_to_be32(
prdf->reg_d1.reg_desc.count = cpu_to_be32(ELS_RDF_REG_TAG_CNT);
struct fc_df_desc_fpin_reg_hdr reg_desc; /* descriptor header */
struct dispc_reg_field reg_desc[DISPC_MGR_FLD_NUM];
.reg_desc = {
.reg_desc = {
.reg_desc = {
.reg_desc = {
const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
struct reg_desc *reg;
static void show_reg(const struct reg_desc *rdesc, u32 value)
struct reg_desc info[NR_REGS];