reg_control
kw_write_reg(reg_control, KW_I2C_CTL_STOP);
kw_write_reg(reg_control,
kw_write_reg(reg_control, 0);
kw_write_reg(reg_control, KW_I2C_CTL_XADDR);
iowrite32(cmd_q->qcontrol & ~CMD5_Q_RUN, cmd_q->reg_control);
iowrite32(cmd_q->qcontrol | CMD5_Q_RUN, cmd_q->reg_control);
cmd_q->reg_control = ccp->io_regs +
cmd_q->reg_tail_lo = cmd_q->reg_control + CMD5_Q_TAIL_LO_BASE;
cmd_q->reg_head_lo = cmd_q->reg_control + CMD5_Q_HEAD_LO_BASE;
cmd_q->reg_int_enable = cmd_q->reg_control +
cmd_q->reg_interrupt_status = cmd_q->reg_control +
cmd_q->reg_status = cmd_q->reg_control + CMD5_Q_STATUS_BASE;
cmd_q->reg_int_status = cmd_q->reg_control +
cmd_q->reg_dma_status = cmd_q->reg_control +
cmd_q->reg_dma_read_status = cmd_q->reg_control +
cmd_q->reg_dma_write_status = cmd_q->reg_control +
iowrite32(cmd_q->qcontrol, cmd_q->reg_control);
iowrite32(cmd_q->qcontrol, cmd_q->reg_control);
void __iomem *reg_control;
void __iomem *reg_control;
ch->reg_control = ch->base + FTDMAC020_CH_CSR;
ch->reg_control = ch->base + PL080_CH_CONTROL;
writel_relaxed(val, phychan->reg_control);
writel_relaxed(lli[PL080_LLI_CCTL], phychan->reg_control);
val = readl(phychan->reg_control);
val = readl(phychan->reg_control);
phychan->reg_control);
val = readl(ch->reg_control);
writel(val, ch->reg_control);
val = readl(ch->reg_control);
writel(val, ch->reg_control);
val = readl(ch->reg_control);
writel(val, ch->reg_control);
val = readl(ch->reg_control);
val = readl(ch->reg_control);
val = readl(ch->reg_control);
cmd_q->reg_control = pt->io_regs + ((i + 1) * AE4_Q_SZ);
cmd_q->reg_control = pt->io_regs + ((i + 1) * AE4_Q_SZ);
writel(CMD_Q_LEN, cmd_q->reg_control + AE4_MAX_IDX_OFF);
writel(lower_32_bits(cmd_q->qdma_tail), cmd_q->reg_control + AE4_Q_BASE_L_OFF);
writel(upper_32_bits(cmd_q->qdma_tail), cmd_q->reg_control + AE4_Q_BASE_H_OFF);
cridx = readl(cmd_q->reg_control + AE4_RD_IDX_OFF);
status = readl(cmd_q->reg_control + AE4_INTR_STS_OFF);
writel(status, cmd_q->reg_control + AE4_INTR_STS_OFF);
regval = readl(cmd_q->reg_control + 0x4);
regval = ioread32(cmd_q->reg_control + 0x000C);
iowrite32(tail, cmd_q->reg_control + 0x0008);
status = ioread32(cmd_q->reg_control + 0x0010);
cmd_q->q_status = ioread32(cmd_q->reg_control + 0x0100);
cmd_q->q_int_status = ioread32(cmd_q->reg_control + 0x0104);
iowrite32(status, cmd_q->reg_control + 0x0010);
cmd_q->reg_control = pt->io_regs + CMD_Q_STATUS_INCR;
iowrite32(cmd_q->qcontrol, cmd_q->reg_control);
ioread32(cmd_q->reg_control + 0x0104);
ioread32(cmd_q->reg_control + 0x0100);
iowrite32(SUPPORTED_INTERRUPTS, cmd_q->reg_control + 0x0010);
iowrite32((u32)dma_addr_lo, cmd_q->reg_control + 0x0004);
iowrite32((u32)dma_addr_lo, cmd_q->reg_control + 0x0008);
iowrite32(cmd_q->qcontrol, cmd_q->reg_control);
iowrite32(SUPPORTED_INTERRUPTS, cmd_q->reg_control + 0x0010);
ioread32(cmd_q->reg_control + 0x0104);
ioread32(cmd_q->reg_control + 0x0100);
iowrite32(cmd_q->qcontrol | CMD_Q_RUN, cmd_q->reg_control);
iowrite32(cmd_q->qcontrol & ~CMD_Q_RUN, cmd_q->reg_control);
iowrite32(tail, cmd_q->reg_control + 0x0004);
writel(ae4cmd_q->tail_wi, cmd_q->reg_control + AE4_WR_IDX_OFF);
u32 front_wi = readl(cmd_q->reg_control + AE4_WR_IDX_OFF);
u32 rear_ri = readl(cmd_q->reg_control + AE4_RD_IDX_OFF);
iowrite32(SUPPORTED_INTERRUPTS, cmd_q->reg_control + 0x0010);
void __iomem *reg_control;
iowrite32(0, pt->cmd_q.reg_control + 0x000C);
iowrite32(SUPPORTED_INTERRUPTS, pt->cmd_q.reg_control + 0x000C);
led->reg_control, led->brightness);
data->reg_control = res->start;
int reg_control;
pm860x_set_bits(led->i2c, led->reg_control,
pm860x_set_bits(led->i2c, led->reg_control, LED_PWM_MASK,
pm860x_bulk_read(led->i2c, led->reg_control, 3, buf);
pm860x_set_bits(led->i2c, led->reg_control,
u64 reg_control;
reg_control = EHEA_BMASK_SET(H_REG_RPAGE_PAGE_SIZE, pagesize)
reg_control, /* R5 */
u32 reg_control;
if ((irq_status & INT_RISCI) && (chip->reg_control & CTL_ACAP_EN)) {
chip->reg_control |= CTL_DA_IOM_DA | CTL_A_PWRDN;
chip->reg_control &= ~(CTL_DA_IOM_DA | CTL_A_PWRDN);
chip->reg_control |= CTL_A_PWRDN;
snd_bt87x_writel(chip, REG_GPIO_DMA_CTL, chip->reg_control);
chip->reg_control &= ~(CTL_DA_SDR_MASK | CTL_DA_SBR);
chip->reg_control |= decimation << CTL_DA_SDR_SHIFT;
chip->reg_control |= CTL_DA_SBR;
snd_bt87x_writel(chip, REG_GPIO_DMA_CTL, chip->reg_control);
chip->reg_control |= CTL_FIFO_ENABLE | CTL_RISC_ENABLE | CTL_ACAP_EN;
snd_bt87x_writel(chip, REG_GPIO_DMA_CTL, chip->reg_control);
chip->reg_control &= ~(CTL_FIFO_ENABLE | CTL_RISC_ENABLE | CTL_ACAP_EN);
snd_bt87x_writel(chip, REG_GPIO_DMA_CTL, chip->reg_control);
value->value.integer.value[0] = (chip->reg_control & CTL_A_GAIN_MASK) >> CTL_A_GAIN_SHIFT;
old_control = chip->reg_control;
chip->reg_control = (chip->reg_control & ~CTL_A_GAIN_MASK)
snd_bt87x_writel(chip, REG_GPIO_DMA_CTL, chip->reg_control);
changed = old_control != chip->reg_control;
value->value.integer.value[0] = !! (chip->reg_control & CTL_A_G2X);
old_control = chip->reg_control;
chip->reg_control = (chip->reg_control & ~CTL_A_G2X)
snd_bt87x_writel(chip, REG_GPIO_DMA_CTL, chip->reg_control);
changed = chip->reg_control != old_control;
value->value.enumerated.item[0] = (chip->reg_control & CTL_A_SEL_MASK) >> CTL_A_SEL_SHIFT;
old_control = chip->reg_control;
chip->reg_control = (chip->reg_control & ~CTL_A_SEL_MASK)
snd_bt87x_writel(chip, REG_GPIO_DMA_CTL, chip->reg_control);
changed = chip->reg_control != old_control;
chip->reg_control = CTL_A_PWRDN | CTL_DA_ES2 |
snd_bt87x_writel(chip, REG_GPIO_DMA_CTL, chip->reg_control);
chip->reg_control |= chip->board.digital_fmt;