arch/arm/mach-davinci/mux.h

252

extern int davinci_cfg_reg(unsigned long reg_cfg);

arch/arm/mach-davinci/mux.h

255

static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; }

drivers/ata/pata_octeon_cf.c

105

reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));

drivers/ata/pata_octeon_cf.c

106

reg_cfg.s.dmack = 0; /* Don't assert DMACK on access */

drivers/ata/pata_octeon_cf.c

107

reg_cfg.s.tim_mult = tim_mult; /* Timing mutiplier */

drivers/ata/pata_octeon_cf.c

108

reg_cfg.s.rd_dly = 0; /* Sample on falling edge of BOOT_OE */

drivers/ata/pata_octeon_cf.c

109

reg_cfg.s.sam = 0; /* Don't combine write and output enable */

drivers/ata/pata_octeon_cf.c

110

reg_cfg.s.we_ext = 0; /* No write enable extension */

drivers/ata/pata_octeon_cf.c

111

reg_cfg.s.oe_ext = 0; /* No read enable extension */

drivers/ata/pata_octeon_cf.c

112

reg_cfg.s.en = 1; /* Enable this region */

drivers/ata/pata_octeon_cf.c

113

reg_cfg.s.orbit = 0; /* Don't combine with previous region */

drivers/ata/pata_octeon_cf.c

114

reg_cfg.s.ale = 0; /* Don't do address multiplexing */

drivers/ata/pata_octeon_cf.c

115

cvmx_write_csr(CVMX_MIO_BOOT_REG_CFGX(cs), reg_cfg.u64);

drivers/ata/pata_octeon_cf.c

87

union cvmx_mio_boot_reg_cfgx reg_cfg;

drivers/clk/mediatek/clk-fhctl.c

101

writel(readl(regs->reg_cfg) | data->frddsx_en, regs->reg_cfg);

drivers/clk/mediatek/clk-fhctl.c

103

writel(readl(regs->reg_cfg) | data->fhctlx_en, regs->reg_cfg);

drivers/clk/mediatek/clk-fhctl.c

131

writel(readl(regs->reg_cfg) | data->sfstrx_en, regs->reg_cfg);

drivers/clk/mediatek/clk-fhctl.c

132

writel(readl(regs->reg_cfg) | data->fhctlx_en, regs->reg_cfg);

drivers/clk/mediatek/clk-fhctl.c

257

writel(0x0, regs.reg_cfg);

drivers/clk/mediatek/clk-fhctl.c

62

readl(regs->reg_cfg), readl(regs->reg_updnlmt),

drivers/clk/mediatek/clk-fhctl.c

73

writel((readl(regs->reg_cfg) & ~(data->frddsx_en)), regs->reg_cfg);

drivers/clk/mediatek/clk-fhctl.c

74

writel((readl(regs->reg_cfg) & ~(data->sfstrx_en)), regs->reg_cfg);

drivers/clk/mediatek/clk-fhctl.c

75

writel((readl(regs->reg_cfg) & ~(data->fhctlx_en)), regs->reg_cfg);

drivers/clk/mediatek/clk-fhctl.c

79

r = readl(regs->reg_cfg);

drivers/clk/mediatek/clk-fhctl.c

82

writel(r, regs->reg_cfg);

drivers/clk/mediatek/clk-fhctl.c

84

r = readl(regs->reg_cfg);

drivers/clk/mediatek/clk-fhctl.c

87

writel(r, regs->reg_cfg);

drivers/clk/mediatek/clk-pllfh.c

133

regs->reg_cfg = fhx_base + offset->offset_cfg;

drivers/clk/mediatek/clk-pllfh.h

50

void __iomem *reg_cfg;

drivers/clk/sprd/pll.c

151

struct reg_cfg *cfg;

drivers/dma/ste_dma40.c

835

writel(lli_src->reg_cfg, base + D40_CHAN_REG_SSCFG);

drivers/dma/ste_dma40.c

840

writel(lli_dst->reg_cfg, base + D40_CHAN_REG_SDCFG);

drivers/dma/ste_dma40_ll.c

137

u32 reg_cfg,

drivers/dma/ste_dma40_ll.c

172

lli->reg_cfg = reg_cfg;

drivers/dma/ste_dma40_ll.c

182

lli->reg_cfg |= BIT(D40_SREG_CFG_TIM_POS);

drivers/dma/ste_dma40_ll.c

184

lli->reg_cfg &= ~BIT(D40_SREG_CFG_TIM_POS);

drivers/dma/ste_dma40_ll.c

214

dma_addr_t lli_phys, dma_addr_t first_phys, u32 reg_cfg,

drivers/dma/ste_dma40_ll.c

250

reg_cfg, info, flags);

drivers/dma/ste_dma40_ll.c

271

u32 reg_cfg,

drivers/dma/ste_dma40_ll.c

299

reg_cfg, info, otherinfo, flags);

drivers/dma/ste_dma40_ll.c

364

u32 reg_cfg,

drivers/dma/ste_dma40_ll.c

370

lli->lcsp13 = reg_cfg;

drivers/dma/ste_dma40_ll.h

345

u32 reg_cfg;

drivers/dma/ste_dma40_ll.h

446

u32 reg_cfg,

drivers/gpu/drm/bridge/lontium-lt9611.c

108

return regmap_multi_reg_write(lt9611->regmap, reg_cfg, ARRAY_SIZE(reg_cfg));

drivers/gpu/drm/bridge/lontium-lt9611.c

114

struct reg_sequence reg_cfg[] = {

drivers/gpu/drm/bridge/lontium-lt9611.c

124

reg_cfg[1].def = 0x03;

drivers/gpu/drm/bridge/lontium-lt9611.c

126

return regmap_multi_reg_write(lt9611->regmap, reg_cfg, ARRAY_SIZE(reg_cfg));

drivers/gpu/drm/bridge/lontium-lt9611.c

177

const struct reg_sequence reg_cfg[] = {

drivers/gpu/drm/bridge/lontium-lt9611.c

204

regmap_multi_reg_write(lt9611->regmap, reg_cfg, ARRAY_SIZE(reg_cfg));

drivers/gpu/drm/bridge/lontium-lt9611.c

227

const struct reg_sequence reg_cfg[] = {

drivers/gpu/drm/bridge/lontium-lt9611.c

241

regmap_multi_reg_write(lt9611->regmap, reg_cfg, ARRAY_SIZE(reg_cfg));

drivers/gpu/drm/bridge/lontium-lt9611.c

348

struct reg_sequence reg_cfg[] = {

drivers/gpu/drm/bridge/lontium-lt9611.c

367

reg_cfg[2].def = 0x73;

drivers/gpu/drm/bridge/lontium-lt9611.c

369

regmap_multi_reg_write(lt9611->regmap, reg_cfg, ARRAY_SIZE(reg_cfg));

drivers/gpu/drm/bridge/lontium-lt9611.c

772

static const struct reg_sequence reg_cfg[] = {

drivers/gpu/drm/bridge/lontium-lt9611.c

783

reg_cfg, ARRAY_SIZE(reg_cfg));

drivers/gpu/drm/bridge/lontium-lt9611.c

96

const struct reg_sequence reg_cfg[] = {

drivers/gpu/drm/imx/dc/dc-cf.c

104

cf->reg_cfg = devm_regmap_init_mmio(dev, base_cfg,

drivers/gpu/drm/imx/dc/dc-cf.c

106

if (IS_ERR(cf->reg_cfg))

drivers/gpu/drm/imx/dc/dc-cf.c

107

return PTR_ERR(cf->reg_cfg);

drivers/gpu/drm/imx/dc/dc-cf.c

56

regmap_write(cf->reg_cfg, STATICCONTROL, SHDEN);

drivers/gpu/drm/imx/dc/dc-cf.c

67

regmap_write(cf->reg_cfg, FRAMEDIMENSIONS, WIDTH(w) | HEIGHT(h));

drivers/gpu/drm/imx/dc/dc-cf.c

72

regmap_write(cf->reg_cfg, CONSTANTCOLOR, 0);

drivers/gpu/drm/imx/dc/dc-cf.c

77

regmap_write(cf->reg_cfg, CONSTANTCOLOR, BLUE(0xff));

drivers/gpu/drm/imx/dc/dc-ed.c

160

regmap_write_bits(ed->reg_cfg, STATICCONTROL, SHDEN, SHDEN);

drivers/gpu/drm/imx/dc/dc-ed.c

165

regmap_write_bits(ed->reg_cfg, STATICCONTROL, KICK_MODE, EXTERNAL);

drivers/gpu/drm/imx/dc/dc-ed.c

170

regmap_write_bits(ed->reg_cfg, STATICCONTROL, PERFCOUNTMODE, 0);

drivers/gpu/drm/imx/dc/dc-ed.c

175

regmap_write_bits(ed->reg_cfg, CONTROL, GAMMAAPPLYENABLE, 0);

drivers/gpu/drm/imx/dc/dc-ed.c

218

ed->reg_cfg = devm_regmap_init_mmio(dev, base_cfg,

drivers/gpu/drm/imx/dc/dc-ed.c

220

if (IS_ERR(ed->reg_cfg))

drivers/gpu/drm/imx/dc/dc-ed.c

221

return PTR_ERR(ed->reg_cfg);

drivers/gpu/drm/imx/dc/dc-fl.c

118

fu->reg_cfg = devm_regmap_init_mmio(dev, base_cfg,

drivers/gpu/drm/imx/dc/dc-fl.c

120

if (IS_ERR(fu->reg_cfg))

drivers/gpu/drm/imx/dc/dc-fl.c

121

return PTR_ERR(fu->reg_cfg);

drivers/gpu/drm/imx/dc/dc-fl.c

65

regmap_write_bits(fu->reg_cfg, LAYERPROPERTY(frac),

drivers/gpu/drm/imx/dc/dc-fl.c

72

regmap_write(fu->reg_cfg, COLORCOMPONENTBITS(frac), bits);

drivers/gpu/drm/imx/dc/dc-fl.c

73

regmap_write(fu->reg_cfg, COLORCOMPONENTSHIFT(frac), shifts);

drivers/gpu/drm/imx/dc/dc-fl.c

78

regmap_write(fu->reg_cfg, FRAMEDIMENSIONS,

drivers/gpu/drm/imx/dc/dc-fu.c

103

regmap_write_bits(fu->reg_cfg, STATICCONTROL,

drivers/gpu/drm/imx/dc/dc-fu.c

110

regmap_write_bits(fu->reg_cfg, STATICCONTROL, SHDLDREQSTICKY_MASK,

drivers/gpu/drm/imx/dc/dc-fu.c

116

regmap_write_bits(fu->reg_cfg, BURSTBUFFERMANAGEMENT, LINEMODE_MASK,

drivers/gpu/drm/imx/dc/dc-fu.c

122

regmap_write_bits(fu->reg_cfg, BURSTBUFFERMANAGEMENT,

drivers/gpu/drm/imx/dc/dc-fu.c

135

regmap_write_bits(fu->reg_cfg, BURSTBUFFERMANAGEMENT,

drivers/gpu/drm/imx/dc/dc-fu.c

142

regmap_write(fu->reg_cfg, fu->reg_baseaddr[frac], baddr);

drivers/gpu/drm/imx/dc/dc-fu.c

147

regmap_write_bits(fu->reg_cfg, fu->reg_sourcebufferattributes[frac],

drivers/gpu/drm/imx/dc/dc-fu.c

154

regmap_write_bits(fu->reg_cfg, fu->reg_sourcebufferattributes[frac],

drivers/gpu/drm/imx/dc/dc-fu.c

161

regmap_write(fu->reg_cfg, fu->reg_sourcebufferdimension[frac],

drivers/gpu/drm/imx/dc/dc-fu.c

168

regmap_write(fu->reg_cfg, fu->reg_layeroffset[frac],

drivers/gpu/drm/imx/dc/dc-fu.c

175

regmap_write(fu->reg_cfg, fu->reg_clipwindowoffset[frac],

drivers/gpu/drm/imx/dc/dc-fu.c

182

regmap_write(fu->reg_cfg, fu->reg_clipwindowdimensions[frac],

drivers/gpu/drm/imx/dc/dc-fu.c

189

regmap_write(fu->reg_cfg, fu->reg_layerproperty[frac], 0);

drivers/gpu/drm/imx/dc/dc-fu.c

190

regmap_write(fu->reg_cfg, fu->reg_constantcolor[frac], 0);

drivers/gpu/drm/imx/dc/dc-fu.c

195

regmap_write_bits(fu->reg_cfg, fu->reg_layerproperty[frac],

drivers/gpu/drm/imx/dc/dc-fu.c

201

regmap_write_bits(fu->reg_cfg, fu->reg_layerproperty[frac],

drivers/gpu/drm/imx/dc/dc-fu.c

98

regmap_write_bits(fu->reg_cfg, STATICCONTROL, SHDEN, SHDEN);

drivers/gpu/drm/imx/dc/dc-fu.h

103

struct regmap *reg_cfg;

drivers/gpu/drm/imx/dc/dc-fw.c

100

regmap_write(fu->reg_cfg, COLORCOMPONENTBITS(frac), bits);

drivers/gpu/drm/imx/dc/dc-fw.c

101

regmap_write(fu->reg_cfg, COLORCOMPONENTSHIFT(frac), shifts);

drivers/gpu/drm/imx/dc/dc-fw.c

106

regmap_write(fu->reg_cfg, FRAMEDIMENSIONS,

drivers/gpu/drm/imx/dc/dc-fw.c

155

fu->reg_cfg = devm_regmap_init_mmio(dev, base_cfg,

drivers/gpu/drm/imx/dc/dc-fw.c

157

if (IS_ERR(fu->reg_cfg))

drivers/gpu/drm/imx/dc/dc-fw.c

158

return PTR_ERR(fu->reg_cfg);

drivers/gpu/drm/imx/dc/dc-fw.c

88

regmap_write_bits(fu->reg_cfg, CONTROL, INPUTSELECT_MASK,

drivers/gpu/drm/imx/dc/dc-fw.c

90

regmap_write_bits(fu->reg_cfg, CONTROL, RASTERMODE_MASK,

drivers/gpu/drm/imx/dc/dc-fw.c

93

regmap_write_bits(fu->reg_cfg, LAYERPROPERTY(frac),

drivers/gpu/drm/imx/dc/dc-lb.c

193

regmap_write_bits(lb->reg_cfg, STATICCONTROL, SHDEN, SHDEN);

drivers/gpu/drm/imx/dc/dc-lb.c

198

regmap_write_bits(lb->reg_cfg, STATICCONTROL, SHDTOKSEL_MASK,

drivers/gpu/drm/imx/dc/dc-lb.c

204

regmap_write_bits(lb->reg_cfg, STATICCONTROL, SHDLDSEL_MASK,

drivers/gpu/drm/imx/dc/dc-lb.c

210

regmap_write_bits(lb->reg_cfg, CONTROL, CTRL_MODE_MASK, mode);

drivers/gpu/drm/imx/dc/dc-lb.c

221

regmap_write(lb->reg_cfg, BLENDCONTROL, val);

drivers/gpu/drm/imx/dc/dc-lb.c

226

regmap_write(lb->reg_cfg, POSITION, XPOS(x) | YPOS(y));

drivers/gpu/drm/imx/dc/dc-lb.c

271

lb->reg_cfg = devm_regmap_init_mmio(dev, base_cfg,

drivers/gpu/drm/imx/dc/dc-lb.c

273

if (IS_ERR(lb->reg_cfg))

drivers/gpu/drm/imx/dc/dc-lb.c

274

return PTR_ERR(lb->reg_cfg);

drivers/gpu/drm/imx/dc/dc-pe.h

49

struct regmap *reg_cfg;

drivers/gpu/drm/imx/dc/dc-pe.h

56

struct regmap *reg_cfg;

drivers/gpu/drm/imx/dc/dc-pe.h

63

struct regmap *reg_cfg;

drivers/iommu/sprd-iommu.c

214

unsigned int reg_cfg;

drivers/iommu/sprd-iommu.c

218

reg_cfg = SPRD_EX_CFG;

drivers/iommu/sprd-iommu.c

220

reg_cfg = SPRD_VAU_CFG;

drivers/iommu/sprd-iommu.c

224

sprd_iommu_update_bits(sdev, reg_cfg, mask, 0, val);

drivers/net/wireless/marvell/mwifiex/fw.h

2443

struct host_cmd_ds_chan_region_cfg reg_cfg;

drivers/net/wireless/marvell/mwifiex/sta_cmd.c

1712

struct host_cmd_ds_chan_region_cfg *reg = &cmd->params.reg_cfg;

drivers/net/wireless/marvell/mwifiex/sta_cmdresp.c

1129

struct host_cmd_ds_chan_region_cfg *reg = &resp->params.reg_cfg;

drivers/net/wireless/ralink/rt2x00/rt2800lib.c

1317

u32 reg_cfg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);

drivers/net/wireless/ralink/rt2x00/rt2800lib.c

1320

if (rt2x00_get_field32(reg_cfg, WPDMA_GLO_CFG_RX_DMA_BUSY) &&

drivers/net/wireless/ralink/rt2x00/rt2800lib.c

1326

if (rt2x00_get_field32(reg_cfg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&

drivers/net/wireless/realtek/rtw88/sdio.c

161

u32 reg_cfg;

drivers/net/wireless/realtek/rtw88/sdio.c

165

reg_cfg = rtw_sdio_to_bus_offset(rtwdev, REG_SDIO_INDIRECT_REG_CFG);

drivers/net/wireless/realtek/rtw88/sdio.c

168

reg_cfg, &ret);

drivers/net/wireless/realtek/rtw88/sdio.c

173

tmp = sdio_readb(rtwsdio->sdio_func, reg_cfg + 2, &ret);

drivers/regulator/rt5759-regulator.c

214

struct regulator_config reg_cfg;

drivers/regulator/rt5759-regulator.c

246

memset(&reg_cfg, 0, sizeof(reg_cfg));

drivers/regulator/rt5759-regulator.c

247

reg_cfg.dev = priv->dev;

drivers/regulator/rt5759-regulator.c

248

reg_cfg.of_node = np;

drivers/regulator/rt5759-regulator.c

249

reg_cfg.init_data = of_get_regulator_init_data(priv->dev, np, reg_desc);

drivers/regulator/rt5759-regulator.c

250

reg_cfg.regmap = priv->regmap;

drivers/regulator/rt5759-regulator.c

252

rdev = devm_regulator_register(priv->dev, reg_desc, &reg_cfg);

drivers/regulator/rtq6752-regulator.c

222

struct regulator_config reg_cfg = {};

drivers/regulator/rtq6752-regulator.c

255

reg_cfg.dev = &i2c->dev;

drivers/regulator/rtq6752-regulator.c

256

reg_cfg.regmap = priv->regmap;

drivers/regulator/rtq6752-regulator.c

257

reg_cfg.driver_data = priv;

drivers/regulator/rtq6752-regulator.c

262

&reg_cfg);

include/linux/soc/ti/omap1-mux.h

306

extern int omap_cfg_reg(unsigned long reg_cfg);

include/linux/soc/ti/omap1-mux.h

308

static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; }