reg_b
int displ, i, res, reg_b, nsaved = 0;
reg_b = (insn >> 16) & 0x1f;
task_thread_info(child)->bpt_addr[nsaved++] = get_reg(child, reg_b);
int reg_d, reg_b;
reg_b = CMOS_READ(RTC_REG_B) & 0x7f;
reg_b |= 2;
CMOS_WRITE(reg_b, RTC_REG_B);
CMOS_READ(RTC_REG_B) == reg_b) {
#define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \
_PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
#define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
_MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b)))
u32 mapped_obj_id, reg_b, zone_restore_id;
reg_b = be32_to_cpu(cqe->ft_metadata);
mapped_obj_id = reg_b & MLX5E_TC_TABLE_CHAIN_TAG_MASK;
zone_restore_id = (reg_b >> MLX5_REG_MAPPING_MOFFSET(NIC_ZONE_RESTORE_TO_REG)) &
u32 chain, reg_b;
reg_b = be32_to_cpu(cqe->ft_metadata);
if (reg_b >> (MLX5E_TC_TABLE_CHAIN_TAG_BITS + ESW_ZONE_ID_BITS))
chain = reg_b & MLX5E_TC_TABLE_CHAIN_TAG_MASK;
reg_b(src));
emit_ld_field(nfp_prog, reg, mask, reg_b(src), sc, shf);
ALU_OP_NOT, reg_b(dst));
emit_alu(nfp_prog, reg_both(dst), reg_a(dst), alu_op, reg_b(src));
reg_a(dst + 1), alu_op, reg_b(src + 1));
emit_alu(nfp_prog, reg_both(dst), reg_a(dst), alu_op, reg_b(src));
emit_alu(nfp_prog, reg_none(), reg_a(dst), alu_op, reg_b(src));
emit_alu(nfp_prog, reg_none(), reg_a(areg), ALU_OP_SUB, reg_b(breg));
reg_a(areg + 1), ALU_OP_SUB_C, reg_b(breg + 1));
multiplier = reg_b(insn->src_reg * 2);
BUILD_BUG_ON(plen_reg(nfp_prog) != reg_b(STATIC_REG_PKT_LEN));
emit_csr_wr(nfp_prog, reg_b(2 * 2), NFP_CSR_ACT_LM_ADDR0);
emit_csr_wr(nfp_prog, reg_b(3 * 2), NFP_CSR_ACT_LM_ADDR2);
wrp_immed_relo(nfp_prog, reg_b(0), ret_tgt, RELO_IMMED_REL);
wrp_immed_relo(nfp_prog, reg_b(0), ret_tgt, RELO_IMMED_REL);
pv_qsel_val(nfp_prog), 0x1, reg_b(meta->insn.src_reg * 2),
reg_b(insn->src_reg * 2));
reg_b(insn->src_reg * 2 + 1));
reg_b(insn->src_reg * 2));
reg_b(insn->src_reg * 2 + 1));
ALU_OP_SUB, reg_b(insn->dst_reg * 2));
ALU_OP_SUB_C, reg_b(insn->dst_reg * 2 + 1));
SHF_OP_NONE, reg_b(dst), SHF_SC_R_DSHF,
reg_b(dst), SHF_SC_L_SHF, shift_amt);
reg_b(dst), SHF_SC_L_SHF, shift_amt - 32);
reg_b(src));
reg_b(dst), SHF_SC_R_DSHF);
reg_b(dst), SHF_SC_L_SHF);
reg_b(dst), SHF_SC_L_SHF);
reg_b(dst), SHF_SC_R_DSHF, shift_amt);
reg_b(dst + 1), SHF_SC_R_SHF, shift_amt);
reg_b(dst + 1), SHF_SC_R_SHF, shift_amt - 32);
reg_b(dst + 1), SHF_SC_R_SHF);
reg_b(dst), SHF_SC_R_DSHF);
reg_b(dst + 1), SHF_SC_R_SHF);
reg_b(dst), SHF_SC_R_DSHF, shift_amt);
reg_b(dst + 1), SHF_SC_R_SHF, shift_amt);
reg_b(dst + 1), SHF_SC_R_SHF, 31);
reg_b(dst + 1), SHF_SC_R_SHF, shift_amt - 32);
reg_b(dst + 1), SHF_SC_R_SHF, 31);
emit_alu(nfp_prog, reg_none(), reg_a(src), ALU_OP_OR, reg_b(dst + 1));
reg_b(dst + 1), SHF_SC_R_SHF);
emit_alu(nfp_prog, reg_none(), reg_a(src), ALU_OP_OR, reg_b(dst + 1));
reg_b(dst + 1), SHF_SC_R_SHF);
reg_b(dst + 1), SHF_SC_R_SHF, 31);
emit_alu(nfp_prog, reg_both(dst), reg_imm(0), ALU_OP_SUB, reg_b(dst));
reg_b(dst), SHF_SC_R_SHF, shift_amt);
emit_alu(nfp_prog, reg_none(), reg_a(src), ALU_OP_OR, reg_b(dst));
reg_b(dst), SHF_SC_R_SHF);
reg_b(dst), SHF_SC_R_SHF, shift_amt);
reg_b(dst), SHF_SC_R_SHF);
reg_b(dst), SHF_SC_L_SHF, shift_amt);
emit_ld_field(nfp_prog, reg_both(gpr), 0x9, reg_b(gpr),
wrp_mov(nfp_prog, imm_a(nfp_prog), reg_b(gpr + 1));
max_imm, ALU_OP_SUB, reg_b(src_gpr));
reg_imm(0), ALU_OP_SUB_C, reg_b(src_gpr + 1));
addrb = reg_b(dst_gpr + 1);
wrp_reg_or_subpart(nfp_prog, prev_alu, reg_b(src_gpr), 2, 2);
or2 = reg_b(insn->dst_reg * 2 + 1);
reg_b(insn->dst_reg * 2));
ALU_OP_OR, reg_b(insn->dst_reg * 2 + 1));
ALU_OP_XOR, reg_b(insn->src_reg * 2));
reg_b(insn->src_reg * 2 + 1));
emit_alu(nfp_prog, reg_none(), reg_imm(7), ALU_OP_SUB, reg_b(0));
wrp_immed(nfp_prog, reg_b(2), 0x41221211);
wrp_immed(nfp_prog, reg_b(3), 0x41001211);
reg_none(), SHF_OP_NONE, reg_b(0), SHF_SC_L_SHF, 2);
reg_imm(0xf), SHF_OP_AND, reg_b(2), SHF_SC_R_SHF, 0);
emit_shf(nfp_prog, reg_b(2),
reg_imm(0xf), SHF_OP_AND, reg_b(3), SHF_SC_R_SHF, 0);
emit_shf(nfp_prog, reg_b(2),
reg_a(2), SHF_OP_OR, reg_b(2), SHF_SC_L_SHF, 4);
emit_ld_field(nfp_prog, reg_a(0), 0xc, reg_b(2), SHF_SC_L_SHF, 16);
emit_alu(nfp_prog, reg_none(), reg_imm(3), ALU_OP_SUB, reg_b(0));
wrp_immed(nfp_prog, reg_b(2), 0x44112282);
reg_none(), SHF_OP_NONE, reg_b(0), SHF_SC_L_SHF, 3);
emit_shf(nfp_prog, reg_b(2),
reg_imm(0xff), SHF_OP_AND, reg_b(2), SHF_SC_R_SHF, 0);
emit_ld_field(nfp_prog, reg_a(0), 0xc, reg_b(2), SHF_SC_L_SHF, 16);
wrp_mov(nfp_prog, reg_lm(0, 1 + idx), reg_b(adj));
wrp_mov(nfp_prog, reg_lm(0, 1 + idx + 1), reg_b(adj + 1));
wrp_mov(nfp_prog, reg_both(dst), reg_b(src));
*regb = reg_b(src_gpr + 1);
emit_alu(nfp_prog, imm_b(nfp_prog), reg_b(src_gpr + 1), ALU_OP_ADD_C,
#define plen_reg(np) reg_b(STATIC_REG_PKT_LEN)
#define imm_b(np) reg_b(STATIC_REG_IMM)
#define imma_b(np) reg_b(STATIC_REG_IMMA)
u8 reg_a, reg_b;
reg_b = (u8)rtw_read_rf(rtwdev, RF_PATH_B, 0x00, 0xf0000);
} while ((reg_a == 2 || reg_b == 2) && count < 2500);
ret = da9055_reg_read(regulator->da9055, info->volt.reg_b);
return da9055_reg_update(regulator->da9055, volt.reg_b,
ret = da9055_reg_read(regulator->da9055, volt.reg_b);
return da9055_reg_update(regulator->da9055, info->volt.reg_b,
return da9055_reg_update(regulator->da9055, info->volt.reg_b,
.reg_b = DA9055_REG_VBCORE_B + DA9055_ID_##_id, \
.reg_b = DA9055_REG_VBCORE_B + DA9055_ID_##_id, \
int reg_b;