regUVD_VCPU_CACHE_OFFSET1
regUVD_VCPU_CACHE_OFFSET1),
WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0);
VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
regUVD_VCPU_CACHE_OFFSET1), 0);
WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET1, 0);
VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0);
VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0);
VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET1, 0);
VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
regUVD_VCPU_CACHE_OFFSET1), 0);