regUVD_VCPU_CACHE_OFFSET0
regUVD_VCPU_CACHE_OFFSET0),
regUVD_VCPU_CACHE_OFFSET0),
WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0);
WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0),
regUVD_VCPU_CACHE_OFFSET0), 0);
regUVD_VCPU_CACHE_OFFSET0),
WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0, 0);
WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0,
VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
VCN, 0, regUVD_VCPU_CACHE_OFFSET0),
WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0);
WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0),
WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0);
WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0),
WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0, 0);
WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0,
VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
VCN, 0, regUVD_VCPU_CACHE_OFFSET0),
regUVD_VCPU_CACHE_OFFSET0), 0);
regUVD_VCPU_CACHE_OFFSET0),