drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1105

WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1108

WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1109

ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1295

WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1298

WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1299

ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1582

tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1775

return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1796

WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr));

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

73

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1341

WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1347

ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1379

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1569

regUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1635

WREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

67

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

975

WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

976

ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1018

WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1021

WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1022

ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1208

WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1211

WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1212

ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1244

tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1439

return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1460

WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr));

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

73

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

1163

return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

1184

WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr));

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

57

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

775

WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

778

WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

779

ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

936

WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

939

WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

940

ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

976

tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1106

WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1109

WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, tmp);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1110

ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1150

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1278

return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1299

WREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

60

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

761

WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

764

WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, tmp);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

765

ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR);