regUVD_RB_BASE_HI
WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI),
WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI,
SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI),
WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI,
WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI),
SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI),
WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI),
WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));