drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1006

WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1009

tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1012

WREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS, tmp);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1578

SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1585

SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1589

WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1714

ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 0x1,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1727

SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

57

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

666

data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

672

WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

692

data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

695

WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1375

SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1382

SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1386

WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1510

ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 0x1,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

51

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

857

WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 1,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

860

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

863

WREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS, tmp);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1240

SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1247

SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1251

WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1377

ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 0x1,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1390

SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

57

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

620

data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

625

WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

643

data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

646

WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

921

WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

924

tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

927

WREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS, tmp);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

1105

ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 0x1,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

41

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

587

data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

593

WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

612

data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

615

WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

705

WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

709

tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

712

WREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS, tmp);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

972

SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

980

WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1146

SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1154

WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

44

SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

681

WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 1,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

685

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

687

WREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS, tmp);